Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.12.1.454

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
Wed Oct 25 21:17:52 2023


Command Line:  synthesis -f Kurs19_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs19/promote.xml 

Synthesis options:
The -a option is MachXO2.
The -s option is 5.
The -t option is TQFP100.
The -d option is LCMXO2-1200HC.
Using package TQFP100.
Using performance grade 5.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-1200HC

### Package : TQFP100

### Speed   : 5

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
Top-level module name = top.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Lattice/Kurs19 (searchpath added)
-p C:/lscc/diamond/3.12/ispfpga/xo2c00/data (searchpath added)
-p C:/Lattice/Kurs19/impl1 (searchpath added)
-p C:/Lattice/Kurs19 (searchpath added)
Verilog design file = C:/Lattice/Kurs19/impl1/source/top.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/decoder_7seg.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/display_multiplex.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/strobe_generator.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/strobe_generator_ticks.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/uart_rx.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/synchronizer.v
Verilog design file = C:/Lattice/Kurs19/impl1/source/edge_detector.v
NGD file = Kurs19_impl1.ngd
-sdc option: SDC file input is C:/Lattice/Kurs19/impl1/source/timing.ldc.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
Analyzing Verilog file c:/lattice/kurs19/impl1/source/top.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/decoder_7seg.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/display_multiplex.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/strobe_generator.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/strobe_generator_ticks.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/uart_rx.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/synchronizer.v. VERI-1482
Analyzing Verilog file c:/lattice/kurs19/impl1/source/edge_detector.v. VERI-1482
Analyzing Verilog file C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Top module name (Verilog): top
INFO - synthesis: c:/lattice/kurs19/impl1/source/top.v(4): compiling module top. VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/uart_rx.v(4): compiling module UartRx(CLOCK_HZ=25000000). VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/synchronizer.v(4): compiling module Synchronizer. VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/strobe_generator_ticks.v(4): compiling module StrobeGeneratorTicks(TICKS=108). VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/edge_detector.v(4): compiling module EdgeDetector. VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/display_multiplex.v(4): compiling module DisplayMultiplex(CLOCK_HZ=25000000). VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000). VERI-1018
INFO - synthesis: c:/lattice/kurs19/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Top-level module name = top.



GSR instance connected to net Reset_c.
Writing LPF file Kurs19_impl1.lpf.
Results of NGD DRC are available in top_drc.log.
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.12/ispfpga/or5g00/data/orc5glib.ngl'...
All blocks are expanded and NGD expansion is successful.
Writing NGD file Kurs19_impl1.ngd.

################### Begin Area Report (top)######################
Number of register bits => 85 of 1520 (5 % )
CCU2D => 8
FD1P3AX => 52
FD1P3IX => 6
FD1S3AX => 5
FD1S3IX => 9
FD1S3JX => 13
GSR => 1
IB => 3
L6MUX21 => 4
LUT4 => 93
OB => 16
PFUMX => 10
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 1
  Net : Clock_c, loads : 85
Clock Enable Nets
Number of Clock Enables: 7
Top 7 highest fanout Clock Enables:
  Net : UartRx_Inst/Clock_c_enable_14, loads : 8
  Net : UartRx_Inst/Clock_c_enable_21, loads : 8
  Net : UartRx_Inst/Busy_N_73, loads : 3
  Net : UartRx_Inst/Clock_c_enable_6, loads : 1
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : UartRx_Inst/RxDone, loads : 31
  Net : DisplayMultiplex0/TempData_3_N_136_2, loads : 31
  Net : DisplayMultiplex0/TempData_3_N_136_3, loads : 20
  Net : DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178, loads : 16
  Net : DisplayMultiplex0/TempData_3_N_136_4, loads : 14
  Net : UartRx_Inst/Clock_c_enable_14, loads : 8
  Net : UartRx_Inst/Clock_c_enable_21, loads : 8
  Net : UartRx_Inst/Busy, loads : 8
  Net : UartRx_Inst/StrobeGeneratorTicks_inst/Counter_0, loads : 8
  Net : DisplayMultiplex0/Enable, loads : 7
################### End Clock Report ##################

Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 40.000000          |             |             |
-waveform { 0.000000 20.000000 } -name  |             |             |
Clock [ get_ports { Clock } ]           |   25.000 MHz|  155.400 MHz|     4  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.


Peak Memory Usage: 55.648  MB

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Elapsed CPU time for LSE flow : 0.266  secs
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