Place & Route TRACE Report

Loading design for application trce from file kurs19_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Wed Oct 25 21:18:00 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs19_impl1.twr -gui -msgset C:/Lattice/Kurs19/promote.xml Kurs19_impl1.ncd Kurs19_impl1.prf 
Design file:     kurs19_impl1.ncd
Preference file: kurs19_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------

Preference Summary

  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 490 items scored, 0 timing errors detected. Report: 172.236MHz is the maximum frequency for this preference.
  • PERIOD PORT "Clock" 40.000000 ns HIGH 20.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 490 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 34.194ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i7 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i4 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i3 Delay: 5.558ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.558ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_5 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.194ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13A.CLK to R7C13A.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 (from Clock_c) ROUTE 2 1.362 R7C13A.Q0 to R8C13C.B1 DisplayMultiplex0/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.452 R8C13C.B1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12C.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.558 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C13A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.194ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i7 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i0 (to Clock_c +) Delay: 5.558ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.558ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_7 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.194ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13A.CLK to R7C13A.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 (from Clock_c) ROUTE 2 1.362 R7C13A.Q0 to R8C13C.B1 DisplayMultiplex0/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.452 R8C13C.B1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12A.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.558 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C13A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.194ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i7 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i2 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i1 Delay: 5.558ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.558ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_6 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.194ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13A.CLK to R7C13A.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 (from Clock_c) ROUTE 2 1.362 R7C13A.Q0 to R8C13C.B1 DisplayMultiplex0/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.452 R8C13C.B1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12B.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.558 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C13A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.194ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i7 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i6 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i5 Delay: 5.558ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.558ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_4 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.194ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_3 to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C13A.CLK to R7C13A.Q0 DisplayMultiplex0/StrobeGenerator0/SLICE_3 (from Clock_c) ROUTE 2 1.362 R7C13A.Q0 to R8C13C.B1 DisplayMultiplex0/StrobeGenerator0/Counter_7 CTOF_DEL --- 0.452 R8C13C.B1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12D.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.558 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C13A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.209ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/Counter_99__i0 (from Clock_c +) Destination: FF Data in UartRx_Inst/Data_o_i0_i1 (to Clock_c +) FF UartRx_Inst/Data_o_i0_i0 Delay: 5.542ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.542ns physical path delay UartRx_Inst/SLICE_33 to UartRx_Inst/SLICE_78 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 34.209ns Physical Path Details: Data path UartRx_Inst/SLICE_33 to UartRx_Inst/SLICE_78: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C16B.CLK to R7C16B.Q0 UartRx_Inst/SLICE_33 (from Clock_c) ROUTE 7 1.294 R7C16B.Q0 to R8C16D.B0 UartRx_Inst/Counter_0 CTOF_DEL --- 0.452 R8C16D.B0 to R8C16D.F0 UartRx_Inst/SLICE_69 ROUTE 1 0.384 R8C16D.F0 to R8C16D.C1 UartRx_Inst/n7 CTOF_DEL --- 0.452 R8C16D.C1 to R8C16D.F1 UartRx_Inst/SLICE_69 ROUTE 3 0.862 R8C16D.F1 to R8C16B.A0 UartRx_Inst/Busy_N_73 CTOF_DEL --- 0.452 R8C16B.A0 to R8C16B.F0 UartRx_Inst/SLICE_40 ROUTE 4 1.237 R8C16B.F0 to R8C18B.CE UartRx_Inst/Clock_c_enable_14 (to Clock_c) -------- 5.542 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to UartRx_Inst/SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C16B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_78: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R8C18B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.209ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/Counter_99__i0 (from Clock_c +) Destination: FF Data in UartRx_Inst/Data_o_i0_i3 (to Clock_c +) FF UartRx_Inst/Data_o_i0_i2 Delay: 5.542ns (31.8% logic, 68.2% route), 4 logic levels. Constraint Details: 5.542ns physical path delay UartRx_Inst/SLICE_33 to UartRx_Inst/SLICE_75 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 34.209ns Physical Path Details: Data path UartRx_Inst/SLICE_33 to UartRx_Inst/SLICE_75: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C16B.CLK to R7C16B.Q0 UartRx_Inst/SLICE_33 (from Clock_c) ROUTE 7 1.294 R7C16B.Q0 to R8C16D.B0 UartRx_Inst/Counter_0 CTOF_DEL --- 0.452 R8C16D.B0 to R8C16D.F0 UartRx_Inst/SLICE_69 ROUTE 1 0.384 R8C16D.F0 to R8C16D.C1 UartRx_Inst/n7 CTOF_DEL --- 0.452 R8C16D.C1 to R8C16D.F1 UartRx_Inst/SLICE_69 ROUTE 3 0.862 R8C16D.F1 to R8C16B.A0 UartRx_Inst/Busy_N_73 CTOF_DEL --- 0.452 R8C16B.A0 to R8C16B.F0 UartRx_Inst/SLICE_40 ROUTE 4 1.237 R8C16B.F0 to R8C18A.CE UartRx_Inst/Clock_c_enable_14 (to Clock_c) -------- 5.542 (31.8% logic, 68.2% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to UartRx_Inst/SLICE_33: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C16B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_75: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R8C18A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.400ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i4 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i0 (to Clock_c +) Delay: 5.352ns (33.0% logic, 67.0% route), 4 logic levels. Constraint Details: 5.352ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_7 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.400ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C12C.CLK to R7C12C.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_5 (from Clock_c) ROUTE 2 1.156 R7C12C.Q1 to R8C13C.A1 DisplayMultiplex0/StrobeGenerator0/Counter_4 CTOF_DEL --- 0.452 R8C13C.A1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12A.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.352 (33.0% logic, 67.0% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.400ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i4 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i4 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i3 Delay: 5.352ns (33.0% logic, 67.0% route), 4 logic levels. Constraint Details: 5.352ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_5 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.400ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C12C.CLK to R7C12C.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_5 (from Clock_c) ROUTE 2 1.156 R7C12C.Q1 to R8C13C.A1 DisplayMultiplex0/StrobeGenerator0/Counter_4 CTOF_DEL --- 0.452 R8C13C.A1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12C.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.352 (33.0% logic, 67.0% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.400ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i4 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i6 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i5 Delay: 5.352ns (33.0% logic, 67.0% route), 4 logic levels. Constraint Details: 5.352ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_4 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.400ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C12C.CLK to R7C12C.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_5 (from Clock_c) ROUTE 2 1.156 R7C12C.Q1 to R8C13C.A1 DisplayMultiplex0/StrobeGenerator0/Counter_4 CTOF_DEL --- 0.452 R8C13C.A1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12D.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.352 (33.0% logic, 67.0% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 34.400ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DisplayMultiplex0/StrobeGenerator0/Counter_i4 (from Clock_c +) Destination: FF Data in DisplayMultiplex0/StrobeGenerator0/Counter_i2 (to Clock_c +) FF DisplayMultiplex0/StrobeGenerator0/Counter_i1 Delay: 5.352ns (33.0% logic, 67.0% route), 4 logic levels. Constraint Details: 5.352ns physical path delay DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_6 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 34.400ns Physical Path Details: Data path DisplayMultiplex0/StrobeGenerator0/SLICE_5 to DisplayMultiplex0/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R7C12C.CLK to R7C12C.Q1 DisplayMultiplex0/StrobeGenerator0/SLICE_5 (from Clock_c) ROUTE 2 1.156 R7C12C.Q1 to R8C13C.A1 DisplayMultiplex0/StrobeGenerator0/Counter_4 CTOF_DEL --- 0.452 R8C13C.A1 to R8C13C.F1 SLICE_76 ROUTE 1 0.610 R8C13C.F1 to R8C13D.B1 DisplayMultiplex0/StrobeGenerator0/n26 CTOF_DEL --- 0.452 R8C13D.B1 to R8C13D.F1 SLICE_24 ROUTE 1 0.384 R8C13D.F1 to R8C13D.C0 DisplayMultiplex0/StrobeGenerator0/n28 CTOF_DEL --- 0.452 R8C13D.C0 to R8C13D.F0 SLICE_24 ROUTE 9 1.437 R8C13D.F0 to R7C12B.LSR DisplayMultiplex0/StrobeGenerator0/Strobe_o_N_178 (to Clock_c) -------- 5.352 (33.0% logic, 67.0% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DisplayMultiplex0/StrobeGenerator0/SLICE_6: Name Fanout Delay (ns) Site Resource ROUTE 46 2.001 20.PADDI to R7C12B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Report: 172.236MHz is the maximum frequency for this preference. ================================================================================ Preference: PERIOD PORT "Clock" 40.000000 ns HIGH 20.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 33.340ns The internal maximum frequency of the following component is 150.150 MHz Logical Details: Cell type Pin name Component name Destination: PIO PAD Clock Delay: 6.660ns -- based on Minimum Pulse Width Report: 6.660ns is the minimum period for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 25.000 MHz| 172.236 MHz| 4 | | | PERIOD PORT "Clock" 40.000000 ns HIGH | | | 20.000000 ns ; | 40.000 ns| 6.660 ns| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 46 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 490 paths, 1 nets, and 314 connections (60.74% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 Wed Oct 25 21:18:00 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs19_impl1.twr -gui -msgset C:/Lattice/Kurs19/promote.xml Kurs19_impl1.ncd Kurs19_impl1.prf Design file: kurs19_impl1.ncd Preference file: kurs19_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 490 items scored, 0 timing errors detected.
  • PERIOD PORT "Clock" 40.000000 ns HIGH 20.000000 ns (0 errors)
  • 0 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 490 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/RxBuffer__0__i1 (from Clock_c +) Destination: FF Data in UartRx_Inst/Data_o_i0_i0 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay UartRx_Inst/SLICE_73 to UartRx_Inst/SLICE_78 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path UartRx_Inst/SLICE_73 to UartRx_Inst/SLICE_78: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C18C.CLK to R8C18C.Q0 UartRx_Inst/SLICE_73 (from Clock_c) ROUTE 1 0.152 R8C18C.Q0 to R8C18B.M0 UartRx_Inst/RxBuffer_1 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to UartRx_Inst/SLICE_73: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C18C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_78: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C18B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/DUT/R1_0__8 (from Clock_c +) Destination: FF Data in UartRx_Inst/DUT/R2_0__9 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_42 to SLICE_42 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_42 to SLICE_42: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C15B.CLK to R10C15B.Q1 SLICE_42 (from Clock_c) ROUTE 1 0.152 R10C15B.Q1 to R10C15B.M0 UartRx_Inst/DUT/R1_0 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_42: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/RxBuffer__0__i5 (from Clock_c +) Destination: FF Data in UartRx_Inst/Data_o_i0_i4 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay UartRx_Inst/SLICE_40 to UartRx_Inst/SLICE_69 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path UartRx_Inst/SLICE_40 to UartRx_Inst/SLICE_69: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C16B.CLK to R8C16B.Q0 UartRx_Inst/SLICE_40 (from Clock_c) ROUTE 2 0.154 R8C16B.Q0 to R8C16D.M0 UartRx_Inst/RxBuffer_5 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to UartRx_Inst/SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_69: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/RxBuffer__0__i7 (from Clock_c +) Destination: FF Data in UartRx_Inst/Data_o_i0_i6 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_41 to UartRx_Inst/SLICE_74 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_41 to UartRx_Inst/SLICE_74: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C16C.CLK to R8C16C.Q0 SLICE_41 (from Clock_c) ROUTE 2 0.154 R8C16C.Q0 to R8C16A.M0 UartRx_Inst/RxBuffer_7 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_74: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q UartRx_Inst/RxBuffer__0__i7 (from Clock_c +) Destination: FF Data in UartRx_Inst/RxBuffer__0__i6 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_41 to UartRx_Inst/SLICE_40 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_41 to UartRx_Inst/SLICE_40: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C16C.CLK to R8C16C.Q0 SLICE_41 (from Clock_c) ROUTE 2 0.154 R8C16C.Q0 to R8C16B.M1 UartRx_Inst/RxBuffer_7 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_41: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to UartRx_Inst/SLICE_40: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R8C16B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToDisplay_i0_i13 (from Clock_c +) Destination: FF Data in DataToDisplay_i0_i21 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_59 to SLICE_72 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_59 to SLICE_72: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C15C.CLK to R10C15C.Q1 SLICE_59 (from Clock_c) ROUTE 3 0.154 R10C15C.Q1 to R10C15D.M0 DataToDisplay_13 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_59: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C15C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_72: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C15D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToDisplay_i0_i6 (from Clock_c +) Destination: FF Data in DataToDisplay_i0_i14 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_64 to SLICE_61 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_64 to SLICE_61: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C14A.CLK to R10C14A.Q0 SLICE_64 (from Clock_c) ROUTE 3 0.154 R10C14A.Q0 to R10C14D.M0 DataToDisplay_6 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C14A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_61: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C14D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToDisplay_i0_i7 (from Clock_c +) Destination: FF Data in DataToDisplay_i0_i15 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_64 to SLICE_61 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_64 to SLICE_61: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C14A.CLK to R10C14A.Q1 SLICE_64 (from Clock_c) ROUTE 3 0.154 R10C14A.Q1 to R10C14D.M1 DataToDisplay_7 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C14A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_61: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R10C14D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToDisplay_i0_i1 (from Clock_c +) Destination: FF Data in DataToDisplay_i0_i9 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_68 to SLICE_60 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_68 to SLICE_60: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C15A.CLK to R9C15A.Q1 SLICE_68 (from Clock_c) ROUTE 2 0.154 R9C15A.Q1 to R9C15B.M1 DataToDisplay_1 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_68: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R9C15A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R9C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DataToDisplay_i0_i0 (from Clock_c +) Destination: FF Data in DataToDisplay_i0_i8 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_68 to SLICE_60 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_68 to SLICE_60: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C15A.CLK to R9C15A.Q0 SLICE_68 (from Clock_c) ROUTE 2 0.154 R9C15A.Q0 to R9C15B.M0 DataToDisplay_0 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_68: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R9C15A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 46 0.773 20.PADDI to R9C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. ================================================================================ Preference: PERIOD PORT "Clock" 40.000000 ns HIGH 20.000000 ns ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 0.000 ns| 0.304 ns| 1 | | | PERIOD PORT "Clock" 40.000000 ns HIGH | | | 20.000000 ns ; | -| -| 0 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 46 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 490 paths, 1 nets, and 314 connections (60.74% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------