Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Wed Oct 25 21:17:53 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     top
Constraint file: top_temp_lse.sdc 
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 40.000000 -waveform { 0.000000 20.000000 } -name Clock [ get_ports { Clock } ]
            660 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 33.565ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \UartRx_Inst/Counter_99__i0  (from Clock +)
   Destination:    FD1P3AX    SP             \UartRx_Inst/Data_o_i0_i4  (to Clock +)

   Delay:                   6.176ns  (28.3% logic, 71.7% route), 4 logic levels.

 Constraint Details:

      6.176ns data_path \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i4 meets
     40.000ns delay constraint less
      0.259ns LCE_S requirement (totaling 39.741ns) by 33.565ns

 Path Details: \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i4

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \UartRx_Inst/Counter_99__i0 (from Clock)
Route         7   e 1.303                                  \UartRx_Inst/Counter[0]
LUT4        ---     0.448              A to Z              \UartRx_Inst/i2_2_lut
Route         1   e 0.788                                  \UartRx_Inst/n7
LUT4        ---     0.448              A to Z              \UartRx_Inst/i887_4_lut
Route         3   e 1.051                                  \UartRx_Inst/Busy_N_73
LUT4        ---     0.448              B to Z              \UartRx_Inst/i1_2_lut
Route         8   e 1.287                                  \UartRx_Inst/Clock_c_enable_14
                  --------
                    6.176  (28.3% logic, 71.7% route), 4 logic levels.


Passed:  The following path meets requirements by 33.565ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \UartRx_Inst/Counter_99__i0  (from Clock +)
   Destination:    FD1P3AX    SP             \UartRx_Inst/Data_o_i0_i3  (to Clock +)

   Delay:                   6.176ns  (28.3% logic, 71.7% route), 4 logic levels.

 Constraint Details:

      6.176ns data_path \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i3 meets
     40.000ns delay constraint less
      0.259ns LCE_S requirement (totaling 39.741ns) by 33.565ns

 Path Details: \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i3

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \UartRx_Inst/Counter_99__i0 (from Clock)
Route         7   e 1.303                                  \UartRx_Inst/Counter[0]
LUT4        ---     0.448              A to Z              \UartRx_Inst/i2_2_lut
Route         1   e 0.788                                  \UartRx_Inst/n7
LUT4        ---     0.448              A to Z              \UartRx_Inst/i887_4_lut
Route         3   e 1.051                                  \UartRx_Inst/Busy_N_73
LUT4        ---     0.448              B to Z              \UartRx_Inst/i1_2_lut
Route         8   e 1.287                                  \UartRx_Inst/Clock_c_enable_14
                  --------
                    6.176  (28.3% logic, 71.7% route), 4 logic levels.


Passed:  The following path meets requirements by 33.565ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \UartRx_Inst/Counter_99__i0  (from Clock +)
   Destination:    FD1P3AX    SP             \UartRx_Inst/Data_o_i0_i5  (to Clock +)

   Delay:                   6.176ns  (28.3% logic, 71.7% route), 4 logic levels.

 Constraint Details:

      6.176ns data_path \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i5 meets
     40.000ns delay constraint less
      0.259ns LCE_S requirement (totaling 39.741ns) by 33.565ns

 Path Details: \UartRx_Inst/Counter_99__i0 to \UartRx_Inst/Data_o_i0_i5

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \UartRx_Inst/Counter_99__i0 (from Clock)
Route         7   e 1.303                                  \UartRx_Inst/Counter[0]
LUT4        ---     0.448              A to Z              \UartRx_Inst/i2_2_lut
Route         1   e 0.788                                  \UartRx_Inst/n7
LUT4        ---     0.448              A to Z              \UartRx_Inst/i887_4_lut
Route         3   e 1.051                                  \UartRx_Inst/Busy_N_73
LUT4        ---     0.448              B to Z              \UartRx_Inst/i1_2_lut
Route         8   e 1.287                                  \UartRx_Inst/Clock_c_enable_14
                  --------
                    6.176  (28.3% logic, 71.7% route), 4 logic levels.

Report: 6.435 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 40.000000          |             |             |
-waveform { 0.000000 20.000000 } -name  |             |             |
Clock [ get_ports { Clock } ]           |    40.000 ns|     6.435 ns|     4  
                                        |             |             |
--------------------------------------------------------------------------------


All constraints were met.



Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover  694 paths, 139 nets, and 391 connections (63.5% coverage)


Peak memory: 58191872 bytes, TRCE: 45056 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs