Lattice Synthesis Timing Report -------------------------------------------------------------------------------- Lattice Synthesis Timing Report, Version Sat Mar 30 12:06:52 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design: top Constraint file: Report level: verbose report, limited to 3 items per constraint -------------------------------------------------------------------------------- ================================================================================ Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c] 326 items scored, 326 timing errors detected. -------------------------------------------------------------------------------- Error: The following path violates requirements by 4.989ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \DDS_inst/multiplier_inst/FF_63 (from Clock_c +) Destination: FD1P3DX D \DDS_inst/multiplier_inst/FF_12 (to Clock_c +) Delay: 9.843ns (36.0% logic, 64.0% route), 8 logic levels. Constraint Details: 9.843ns data_path \DDS_inst/multiplier_inst/FF_63 to \DDS_inst/multiplier_inst/FF_12 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 4.989ns Path Details: \DDS_inst/multiplier_inst/FF_63 to \DDS_inst/multiplier_inst/FF_12 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DDS_inst/multiplier_inst/FF_63 (from Clock_c) Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_0_2 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Cadd_Multiplier_0_0_1 Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_1_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_2 Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_1_6 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_3 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_3 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_4 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_5 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_5 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_6 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_6 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Cadd_Multiplier_0_0_7 Route 1 e 0.788 \DDS_inst/multiplier_inst/s_Multiplier_0_0_13 -------- 9.843 (36.0% logic, 64.0% route), 8 logic levels. Error: The following path violates requirements by 4.989ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \DDS_inst/multiplier_inst/FF_55 (from Clock_c +) Destination: FD1P3DX D \DDS_inst/multiplier_inst/FF_12 (to Clock_c +) Delay: 9.843ns (36.0% logic, 64.0% route), 8 logic levels. Constraint Details: 9.843ns data_path \DDS_inst/multiplier_inst/FF_55 to \DDS_inst/multiplier_inst/FF_12 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 4.989ns Path Details: \DDS_inst/multiplier_inst/FF_55 to \DDS_inst/multiplier_inst/FF_12 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DDS_inst/multiplier_inst/FF_55 (from Clock_c) Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_0_2 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Cadd_Multiplier_0_0_1 Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_1_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_2 Route 1 e 0.788 \DDS_inst/multiplier_inst/f_Multiplier_0_pp_1_6 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_3 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_3 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_4 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_5 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_5 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Multiplier_0_add_0_6 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_Multiplier_0_0_6 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Cadd_Multiplier_0_0_7 Route 1 e 0.788 \DDS_inst/multiplier_inst/s_Multiplier_0_0_13 -------- 9.843 (36.0% logic, 64.0% route), 8 logic levels. Error: The following path violates requirements by 4.989ns Logical Details: Cell type Pin type Cell name (clock net +/-) Source: FD1P3DX CK \DDS_inst/multiplier_inst/FF_21 (from Clock_c +) Destination: FD1P3DX D \DDS_inst/multiplier_inst/FF_66 (to Clock_c +) Delay: 9.843ns (36.0% logic, 64.0% route), 8 logic levels. Constraint Details: 9.843ns data_path \DDS_inst/multiplier_inst/FF_21 to \DDS_inst/multiplier_inst/FF_66 violates 5.000ns delay constraint less 0.146ns L_S requirement (totaling 4.854ns) by 4.989ns Path Details: \DDS_inst/multiplier_inst/FF_21 to \DDS_inst/multiplier_inst/FF_66 Name Fanout Delay (ns) Pins Resource(Cell.Net) L_CO --- 0.403 CK to Q \DDS_inst/multiplier_inst/FF_21 (from Clock_c) Route 1 e 0.788 \DDS_inst/multiplier_inst/f_s_Multiplier_0_0_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/Cadd_t_Multiplier_0_2_1 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_t_Multiplier_0_2_1 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_2 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_t_Multiplier_0_2_2 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_3 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_t_Multiplier_0_2_3 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_4 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_t_Multiplier_0_2_4 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_5 Route 1 e 0.788 \DDS_inst/multiplier_inst/co_t_Multiplier_0_2_5 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_6 Route 1 e 0.788 \DDS_inst/multiplier_inst/f_s_Multiplier_0_1_15 LUT4 --- 0.448 to \DDS_inst/multiplier_inst/t_Multiplier_0_add_2_7 Route 1 e 0.788 \DDS_inst/multiplier_inst/p_L3_15 -------- 9.843 (36.0% logic, 64.0% route), 8 logic levels. Warning: 9.989 ns is the maximum delay for this constraint. Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock_c] | 5.000 ns| 9.989 ns| 8 * | | | -------------------------------------------------------------------------------- 1 constraints not met. -------------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total -------------------------------------------------------------------------------- \DDS_inst/multiplier_inst/a_ff_2 | 8| 96| 29.45% | | | \DDS_inst/multiplier_inst/a_ff_4 | 8| 96| 29.45% | | | \DDS_inst/multiplier_inst/a_ff_6 | 8| 96| 29.45% | | | \DDS_inst/multiplier_inst/a_ff_0 | 7| 72| 22.09% | | | \FrequencyMeter_inst/DoubleDabble_inst/n| | | 6 | 1| 68| 20.86% | | | \FrequencyMeter_inst/DoubleDabble_inst/n| | | 2143 | 7| 68| 20.86% | | | \FrequencyMeter_inst/DoubleDabble_inst/C| | | lock_c_enable_125 | 32| 64| 19.63% | | | \DDS_inst/multiplier_inst/b_ff_4 | 9| 56| 17.18% | | | \DDS_inst/multiplier_inst/co_t_Multiplie| | | r_0_2_3 | 1| 50| 15.34% | | | \DDS_inst/multiplier_inst/co_Multiplier_| | | 0_0_3 | 1| 48| 14.72% | | | \DDS_inst/multiplier_inst/co_t_Multiplie| | | r_0_2_2 | 1| 46| 14.11% | | | \DDS_inst/multiplier_inst/co_t_Multiplie| | | r_0_2_4 | 1| 46| 14.11% | | | \DDS_inst/multiplier_inst/f_Multiplier_0| | | _pp_1_6 | 1| 46| 14.11% | | | \DDS_inst/multiplier_inst/co_Multiplier_| | | 0_0_4 | 1| 44| 13.50% | | | \DDS_inst/multiplier_inst/co_t_Multiplie| | | r_0_2_1 | 1| 34| 10.43% | | | \DDS_inst/multiplier_inst/co_t_Multiplie| | | r_0_2_5 | 1| 34| 10.43% | | | \DDS_inst/multiplier_inst/f_Multiplier_0| | | _pp_1_4 | 1| 34| 10.43% | | | \FrequencyMeter_inst/DoubleDabble_inst/C| | | ounter[1] | 5| 34| 10.43% | | | \FrequencyMeter_inst/DoubleDabble_inst/C| | | ounter[4] | 2| 34| 10.43% | | | -------------------------------------------------------------------------------- Timing summary: --------------- Timing errors: 326 Score: 679514 Constraints cover 4464 paths, 713 nets, and 1865 connections (88.3% coverage) Peak memory: 70627328 bytes, TRCE: 0 bytes, DLYMAN: 0 bytes CPU_TIME_REPORT: 0 secs