--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2
Wed Mar 27 21:13:03 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design file:     top
Device,speed:    LCMXO2-1200HC,M
Report level:    verbose report, limited to 200 items per preference
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ;
            200 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 

Passed: The following path meets requirements by 0.238ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i8  (from Clock_c +)
   Destination:    SP8KC      Port           DDS_inst/ROM_inst/mux_134(ASIC)  (to Clock_c +)

   Delay:               0.344ns  (38.7% logic, 61.3% route), 1 logic levels.

 Constraint Details:

      0.344ns physical path delay DDS_inst/SLICE_28 to DDS_inst/ROM_inst/mux_134 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.054ns skew requirement (totaling 0.106ns) by 0.238ns

 Physical Path Details:

      Data path DDS_inst/SLICE_28 to DDS_inst/ROM_inst/mux_134:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9A.CLK to       R8C9A.Q0 DDS_inst/SLICE_28 (from Clock_c)
ROUTE         4     0.211       R8C9A.Q0 to EBR_R6C7.AD5   DDS_inst/Accumulator_8 (to Clock_c)
                  --------
                    0.344   (38.7% logic, 61.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/ROM_inst/mux_134:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.827       20.PADDI to EBR_R6C7.CLK   Clock_c
                  --------
                    0.827   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.304ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/SynchronizerA/R1_i2  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/SynchronizerA/R2_i2  (to Clock_c +)

   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.

 Constraint Details:

      0.285ns physical path delay EncoderAmpl_inst/SLICE_219 to EncoderAmpl_inst/SLICE_206 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.304ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_219 to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13B.CLK to      R5C13B.Q1 EncoderAmpl_inst/SLICE_219 (from Clock_c)
ROUTE         1     0.152      R5C13B.Q1 to R5C13D.M1      EncoderAmpl_inst/SynchronizerA/R1_2 (to Clock_c)
                  --------
                    0.285   (46.7% logic, 53.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.304ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/SynchronizerA/R1_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/SynchronizerA/R2_i1  (to Clock_c +)

   Delay:               0.285ns  (46.7% logic, 53.3% route), 1 logic levels.

 Constraint Details:

      0.285ns physical path delay EncoderAmpl_inst/SLICE_219 to EncoderAmpl_inst/SLICE_206 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.304ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_219 to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13B.CLK to      R5C13B.Q0 EncoderAmpl_inst/SLICE_219 (from Clock_c)
ROUTE         1     0.152      R5C13B.Q0 to R5C13D.M0      EncoderAmpl_inst/SynchronizerA/R1_1 (to Clock_c)
                  --------
                    0.285   (46.7% logic, 53.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_219:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.306ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Synchronizer_inst/R2_0__9  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/EdgeDetector_inst/Previous_13  (to Clock_c +)

   Delay:               0.287ns  (46.3% logic, 53.7% route), 1 logic levels.

 Constraint Details:

      0.287ns physical path delay FrequencyMeter_inst/SLICE_181 to FrequencyMeter_inst/SLICE_181 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.306ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_181 to FrequencyMeter_inst/SLICE_181:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13D.CLK to      R8C13D.Q0 FrequencyMeter_inst/SLICE_181 (from Clock_c)
ROUTE         2     0.154      R8C13D.Q0 to R8C13D.M1      SignalSync (to Clock_c)
                  --------
                    0.287   (46.3% logic, 53.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_181:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_181:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.307ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i30  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i30  (to Clock_c +)

   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/SLICE_138 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.307ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/SLICE_138:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15A.CLK to      R9C15A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 (from Clock_c)
ROUTE         5     0.155      R9C15A.Q1 to R9C15B.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_30 (to Clock_c)
                  --------
                    0.288   (46.2% logic, 53.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_138:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.307ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i31  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i31  (to Clock_c +)

   Delay:               0.288ns  (46.2% logic, 53.8% route), 1 logic levels.

 Constraint Details:

      0.288ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 to FrequencyMeter_inst/SLICE_138 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.307ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 to FrequencyMeter_inst/SLICE_138:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15C.CLK to      R9C15C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 (from Clock_c)
ROUTE         4     0.155      R9C15C.Q0 to R9C15B.M1      FrequencyMeter_inst/DoubleDabble_inst/BCD_31 (to Clock_c)
                  --------
                    0.288   (46.2% logic, 53.8% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_138:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.309ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i6  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i6  (to Clock_c +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_214 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_214:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C14A.CLK to      R7C14A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 (from Clock_c)
ROUTE         5     0.157      R7C14A.Q0 to R9C14A.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_6 (to Clock_c)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_214:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.309ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i23  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i23  (to Clock_c +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_210 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_210:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13D.CLK to      R9C13D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 (from Clock_c)
ROUTE         5     0.157      R9C13D.Q0 to R9C11D.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_23 (to Clock_c)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_210:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.309ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i0  (to Clock_c +)

   Delay:               0.290ns  (45.9% logic, 54.1% route), 1 logic levels.

 Constraint Details:

      0.290ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 to SLICE_228 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.309ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 to SLICE_228:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11C.CLK to      R7C11C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 (from Clock_c)
ROUTE         6     0.157      R7C11C.Q0 to R7C12C.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_0 (to Clock_c)
                  --------
                    0.290   (45.9% logic, 54.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_140:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_228:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C12C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.314ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i14  (to Clock_c +)

   Delay:               0.295ns  (45.1% logic, 54.9% route), 1 logic levels.

 Constraint Details:

      0.295ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_198 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.314ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_198:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C10A.CLK to      R9C10A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 (from Clock_c)
ROUTE         5     0.162      R9C10A.Q0 to R9C11A.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_14 (to Clock_c)
                  --------
                    0.295   (45.1% logic, 54.9% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_198:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.316ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i27  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i27  (to Clock_c +)

   Delay:               0.297ns  (44.8% logic, 55.2% route), 1 logic levels.

 Constraint Details:

      0.297ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to SLICE_136 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.316ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to SLICE_136:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 (from Clock_c)
ROUTE         5     0.164      R9C14C.Q0 to R9C14D.M1      FrequencyMeter_inst/DoubleDabble_inst/BCD_27 (to Clock_c)
                  --------
                    0.297   (44.8% logic, 55.2% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_136:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i5  (to Clock_c +)

   Delay:               0.298ns  (44.6% logic, 55.4% route), 1 logic levels.

 Constraint Details:

      0.298ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.317ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 (from Clock_c)
ROUTE         6     0.165      R8C14B.Q1 to R8C14D.M1      FrequencyMeter_inst/DoubleDabble_inst/BCD_5 (to Clock_c)
                  --------
                    0.298   (44.6% logic, 55.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i11  (to Clock_c +)

   Delay:               0.298ns  (44.6% logic, 55.4% route), 1 logic levels.

 Constraint Details:

      0.298ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.317ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 (from Clock_c)
ROUTE         5     0.165      R8C12A.Q1 to R8C12D.M1      FrequencyMeter_inst/DoubleDabble_inst/BCD_11 (to Clock_c)
                  --------
                    0.298   (44.6% logic, 55.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.317ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i10  (to Clock_c +)

   Delay:               0.298ns  (44.6% logic, 55.4% route), 1 logic levels.

 Constraint Details:

      0.298ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.317ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 (from Clock_c)
ROUTE         5     0.165      R8C12A.Q0 to R8C12D.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_10 (to Clock_c)
                  --------
                    0.298   (44.6% logic, 55.4% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_215:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.321ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i4  (to Clock_c +)

   Delay:               0.302ns  (44.0% logic, 56.0% route), 1 logic levels.

 Constraint Details:

      0.302ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.321ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 (from Clock_c)
ROUTE         6     0.169      R8C14B.Q0 to R8C14D.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_4 (to Clock_c)
                  --------
                    0.302   (44.0% logic, 56.0% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_208:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.325ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i11  (from Clock_c +)
   Destination:    SP8KC      Port           DDS_inst/ROM_inst/mux_134(ASIC)  (to Clock_c +)

   Delay:               0.431ns  (30.9% logic, 69.1% route), 1 logic levels.

 Constraint Details:

      0.431ns physical path delay DDS_inst/SLICE_27 to DDS_inst/ROM_inst/mux_134 meets
      0.052ns ADDR_HLD and
      0.000ns delay constraint less
     -0.054ns skew requirement (totaling 0.106ns) by 0.325ns

 Physical Path Details:

      Data path DDS_inst/SLICE_27 to DDS_inst/ROM_inst/mux_134:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9B.CLK to       R8C9B.Q1 DDS_inst/SLICE_27 (from Clock_c)
ROUTE         4     0.298       R8C9B.Q1 to EBR_R6C7.AD8   DDS_inst/Accumulator_11 (to Clock_c)
                  --------
                    0.431   (30.9% logic, 69.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/ROM_inst/mux_134:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.827       20.PADDI to EBR_R6C7.CLK   Clock_c
                  --------
                    0.827   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.338ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/State_FSM_i3  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/Decrement_o_40  (to Clock_c +)

   Delay:               0.281ns  (47.3% logic, 52.7% route), 1 logic levels.

 Constraint Details:

      0.281ns physical path delay EncoderAmpl_inst/SLICE_120 to EncoderAmpl_inst/SLICE_115 meets
     -0.057ns LSR_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.057ns) by 0.338ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_120 to EncoderAmpl_inst/SLICE_115:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13C.CLK to      R5C13C.Q0 EncoderAmpl_inst/SLICE_120 (from Clock_c)
ROUTE         6     0.148      R5C13C.Q0 to R5C13A.LSR     EncoderAmpl_inst/n249 (to Clock_c)
                  --------
                    0.281   (47.3% logic, 52.7% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_115:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.346ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i18  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i18  (to Clock_c +)

   Delay:               0.327ns  (40.7% logic, 59.3% route), 1 logic levels.

 Constraint Details:

      0.327ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_192 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.346ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_192:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13A.CLK to      R8C13A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 (from Clock_c)
ROUTE         5     0.194      R8C13A.Q0 to R7C13A.M0      FrequencyMeter_inst/DoubleDabble_inst/BCD_18 (to Clock_c)
                  --------
                    0.327   (40.7% logic, 59.3% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_192:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.377ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i1  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i1  (to Clock_c +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay DDS_inst/SLICE_33 to DDS_inst/SLICE_33 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path DDS_inst/SLICE_33 to DDS_inst/SLICE_33:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8A.CLK to       R8C8A.Q1 DDS_inst/SLICE_33 (from Clock_c)
ROUTE         1     0.130       R8C8A.Q1 to R8C8A.A1       DDS_inst/n15
CTOF_DEL    ---     0.101       R8C8A.A1 to       R8C8A.F1 DDS_inst/SLICE_33
ROUTE         1     0.000       R8C8A.F1 to R8C8A.DI1      DDS_inst/n84 (to Clock_c)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_33:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_33:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.377ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i5  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i5  (to Clock_c +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay DDS_inst/SLICE_31 to DDS_inst/SLICE_31 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path DDS_inst/SLICE_31 to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8C.CLK to       R8C8C.Q1 DDS_inst/SLICE_31 (from Clock_c)
ROUTE         1     0.130       R8C8C.Q1 to R8C8C.A1       DDS_inst/n11
CTOF_DEL    ---     0.101       R8C8C.A1 to       R8C8C.F1 DDS_inst/SLICE_31
ROUTE         1     0.000       R8C8C.F1 to R8C8C.DI1      DDS_inst/n80 (to Clock_c)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.377ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i4  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i4  (to Clock_c +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay DDS_inst/SLICE_31 to DDS_inst/SLICE_31 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path DDS_inst/SLICE_31 to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8C.CLK to       R8C8C.Q0 DDS_inst/SLICE_31 (from Clock_c)
ROUTE         1     0.130       R8C8C.Q0 to R8C8C.A0       DDS_inst/n12
CTOF_DEL    ---     0.101       R8C8C.A0 to       R8C8C.F0 DDS_inst/SLICE_31
ROUTE         1     0.000       R8C8C.F0 to R8C8C.DI0      DDS_inst/n81 (to Clock_c)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_31:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.377ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i2  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i2  (to Clock_c +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay DDS_inst/SLICE_32 to DDS_inst/SLICE_32 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path DDS_inst/SLICE_32 to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8B.CLK to       R8C8B.Q0 DDS_inst/SLICE_32 (from Clock_c)
ROUTE         1     0.130       R8C8B.Q0 to R8C8B.A0       DDS_inst/n14
CTOF_DEL    ---     0.101       R8C8B.A0 to       R8C8B.F0 DDS_inst/SLICE_32
ROUTE         1     0.000       R8C8B.F0 to R8C8B.DI0      DDS_inst/n83 (to Clock_c)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.377ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i3  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i3  (to Clock_c +)

   Delay:               0.364ns  (64.3% logic, 35.7% route), 2 logic levels.

 Constraint Details:

      0.364ns physical path delay DDS_inst/SLICE_32 to DDS_inst/SLICE_32 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.377ns

 Physical Path Details:

      Data path DDS_inst/SLICE_32 to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8B.CLK to       R8C8B.Q1 DDS_inst/SLICE_32 (from Clock_c)
ROUTE         1     0.130       R8C8B.Q1 to R8C8B.A1       DDS_inst/n13
CTOF_DEL    ---     0.101       R8C8B.A1 to       R8C8B.F1 DDS_inst/SLICE_32
ROUTE         1     0.000       R8C8B.F1 to R8C8B.DI1      DDS_inst/n82 (to Clock_c)
                  --------
                    0.364   (64.3% logic, 35.7% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_32:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i12  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16C.CLK to     R10C16C.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 (from Clock_c)
ROUTE         2     0.132     R10C16C.Q1 to R10C16C.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_12
CTOF_DEL    ---     0.101     R10C16C.A1 to     R10C16C.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95
ROUTE         1     0.000     R10C16C.F1 to R10C16C.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n8 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i8  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/SLICE_76 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16A.CLK to      R7C16A.Q1 FrequencyMeter_inst/SLICE_76 (from Clock_c)
ROUTE         2     0.132      R7C16A.Q1 to R7C16A.A1      FrequencyMeter_inst/Counter_8
CTOF_DEL    ---     0.101      R7C16A.A1 to      R7C16A.F1 FrequencyMeter_inst/SLICE_76
ROUTE         1     0.000      R7C16A.F1 to R7C16A.DI1     FrequencyMeter_inst/n27 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i8  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11A.CLK to      R2C11A.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 (from Clock_c)
ROUTE         2     0.132      R2C11A.Q1 to R2C11A.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_8
CTOF_DEL    ---     0.101      R2C11A.A1 to      R2C11A.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89
ROUTE         1     0.000      R2C11A.F1 to R2C11A.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n22 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i6  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_29 to DDS_inst/SLICE_29 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_29 to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8D.CLK to       R8C8D.Q0 DDS_inst/SLICE_29 (from Clock_c)
ROUTE         4     0.132       R8C8D.Q0 to R8C8D.A0       DDS_inst/Accumulator_6
CTOF_DEL    ---     0.101       R8C8D.A0 to       R8C8D.F0 DDS_inst/SLICE_29
ROUTE         1     0.000       R8C8D.F0 to R8C8D.DI0      DDS_inst/n79 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i3  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/SLICE_78 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15C.CLK to      R7C15C.Q0 FrequencyMeter_inst/SLICE_78 (from Clock_c)
ROUTE         2     0.132      R7C15C.Q0 to R7C15C.A0      FrequencyMeter_inst/Counter_3
CTOF_DEL    ---     0.101      R7C15C.A0 to      R7C15C.F0 FrequencyMeter_inst/SLICE_78
ROUTE         1     0.000      R7C15C.F0 to R7C15C.DI0     FrequencyMeter_inst/n32 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/SLICE_76 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16A.CLK to      R7C16A.Q0 FrequencyMeter_inst/SLICE_76 (from Clock_c)
ROUTE         2     0.132      R7C16A.Q0 to R7C16A.A0      FrequencyMeter_inst/Counter_7
CTOF_DEL    ---     0.101      R7C16A.A0 to      R7C16A.F0 FrequencyMeter_inst/SLICE_76
ROUTE         1     0.000      R7C16A.F0 to R7C16A.DI0     FrequencyMeter_inst/n28 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i11  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_74 to FrequencyMeter_inst/SLICE_74 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_74 to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16C.CLK to      R7C16C.Q0 FrequencyMeter_inst/SLICE_74 (from Clock_c)
ROUTE         2     0.132      R7C16C.Q0 to R7C16C.A0      FrequencyMeter_inst/Counter_11
CTOF_DEL    ---     0.101      R7C16C.A0 to      R7C16C.F0 FrequencyMeter_inst/SLICE_74
ROUTE         1     0.000      R7C16C.F0 to R7C16C.DI0     FrequencyMeter_inst/n24 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i15  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i15  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C10A.CLK to      R9C10A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 (from Clock_c)
ROUTE         5     0.132      R9C10A.Q1 to R9C10A.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_15
CTOF_DEL    ---     0.101      R9C10A.A1 to      R9C10A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_147
ROUTE         1     0.000      R9C10A.F1 to R9C10A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n158 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i24  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i24  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C13A.CLK to      R2C13A.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 (from Clock_c)
ROUTE         2     0.132      R2C13A.Q1 to R2C13A.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_24
CTOF_DEL    ---     0.101      R2C13A.A1 to      R2C13A.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81
ROUTE         1     0.000      R2C13A.F1 to R2C13A.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n6 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i0  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15A.CLK to     R10C15A.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101 (from Clock_c)
ROUTE         2     0.132     R10C15A.Q1 to R10C15A.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_0
CTOF_DEL    ---     0.101     R10C15A.A1 to     R10C15A.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101
ROUTE         1     0.000     R10C15A.F1 to R10C15A.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n20 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_101:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i21  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i21  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12D.CLK to      R2C12D.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 (from Clock_c)
ROUTE         2     0.132      R2C12D.Q0 to R2C12D.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_21
CTOF_DEL    ---     0.101      R2C12D.A0 to      R2C12D.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82
ROUTE         1     0.000      R2C12D.F0 to R2C12D.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n9 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i5  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15D.CLK to     R10C15D.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 (from Clock_c)
ROUTE         2     0.132     R10C15D.Q0 to R10C15D.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_5
CTOF_DEL    ---     0.101     R10C15D.A0 to     R10C15D.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98
ROUTE         1     0.000     R10C15D.F0 to R10C15D.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n15 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i3  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15C.CLK to     R10C15C.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 (from Clock_c)
ROUTE         2     0.132     R10C15C.Q0 to R10C15C.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_3
CTOF_DEL    ---     0.101     R10C15C.A0 to     R10C15C.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99
ROUTE         1     0.000     R10C15C.F0 to R10C15C.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n17 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i4  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10C.CLK to      R2C10C.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 (from Clock_c)
ROUTE         2     0.132      R2C10C.Q1 to R2C10C.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_4
CTOF_DEL    ---     0.101      R2C10C.A1 to      R2C10C.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91
ROUTE         1     0.000      R2C10C.F1 to R2C10C.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n26 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/State_FSM_i2  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay EncoderAmpl_inst/SLICE_120 to EncoderAmpl_inst/SLICE_120 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_120 to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13C.CLK to      R5C13C.Q1 EncoderAmpl_inst/SLICE_120 (from Clock_c)
ROUTE         3     0.132      R5C13C.Q1 to R5C13C.A1      EncoderAmpl_inst/n250
CTOF_DEL    ---     0.101      R5C13C.A1 to      R5C13C.F1 EncoderAmpl_inst/SLICE_120
ROUTE         1     0.000      R5C13C.F1 to R5C13C.DI1     EncoderAmpl_inst/n1978 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i0  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10A.CLK to      R2C10A.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93 (from Clock_c)
ROUTE         2     0.132      R2C10A.Q1 to R2C10A.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_0
CTOF_DEL    ---     0.101      R2C10A.A1 to      R2C10A.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93
ROUTE         1     0.000      R2C10A.F1 to R2C10A.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n30 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_93:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i6  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15D.CLK to     R10C15D.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98 (from Clock_c)
ROUTE         2     0.132     R10C15D.Q1 to R10C15D.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_6
CTOF_DEL    ---     0.101     R10C15D.A1 to     R10C15D.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98
ROUTE         1     0.000     R10C15D.F1 to R10C15D.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n14 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_98:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i15  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i15  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/SLICE_72 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17A.CLK to      R7C17A.Q0 FrequencyMeter_inst/SLICE_72 (from Clock_c)
ROUTE         2     0.132      R7C17A.Q0 to R7C17A.A0      FrequencyMeter_inst/Counter_15
CTOF_DEL    ---     0.101      R7C17A.A0 to      R7C17A.F0 FrequencyMeter_inst/SLICE_72
ROUTE         1     0.000      R7C17A.F0 to R7C17A.DI0     FrequencyMeter_inst/n20 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11A.CLK to      R2C11A.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89 (from Clock_c)
ROUTE         2     0.132      R2C11A.Q0 to R2C11A.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_7
CTOF_DEL    ---     0.101      R2C11A.A0 to      R2C11A.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89
ROUTE         1     0.000      R2C11A.F0 to R2C11A.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n23 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_89:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i19  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i19  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_70 to FrequencyMeter_inst/SLICE_70 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_70 to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17C.CLK to      R7C17C.Q0 FrequencyMeter_inst/SLICE_70 (from Clock_c)
ROUTE         2     0.132      R7C17C.Q0 to R7C17C.A0      FrequencyMeter_inst/Counter_19
CTOF_DEL    ---     0.101      R7C17C.A0 to      R7C17C.F0 FrequencyMeter_inst/SLICE_70
ROUTE         1     0.000      R7C17C.F0 to R7C17C.DI0     FrequencyMeter_inst/n16 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i0  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_80 to FrequencyMeter_inst/SLICE_80 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_80 to FrequencyMeter_inst/SLICE_80:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15A.CLK to      R7C15A.Q1 FrequencyMeter_inst/SLICE_80 (from Clock_c)
ROUTE         2     0.132      R7C15A.Q1 to R7C15A.A1      FrequencyMeter_inst/Counter_0
CTOF_DEL    ---     0.101      R7C15A.A1 to      R7C15A.F1 FrequencyMeter_inst/SLICE_80
ROUTE         1     0.000      R7C15A.F1 to R7C15A.DI1     FrequencyMeter_inst/n35 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_80:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_80:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i23  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i23  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/SLICE_68 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18A.CLK to      R7C18A.Q0 FrequencyMeter_inst/SLICE_68 (from Clock_c)
ROUTE         2     0.132      R7C18A.Q0 to R7C18A.A0      FrequencyMeter_inst/Counter_23
CTOF_DEL    ---     0.101      R7C18A.A0 to      R7C18A.F0 FrequencyMeter_inst/SLICE_68
ROUTE         1     0.000      R7C18A.F0 to R7C18A.DI0     FrequencyMeter_inst/n12 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i20  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i20  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_70 to FrequencyMeter_inst/SLICE_70 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_70 to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17C.CLK to      R7C17C.Q1 FrequencyMeter_inst/SLICE_70 (from Clock_c)
ROUTE         2     0.132      R7C17C.Q1 to R7C17C.A1      FrequencyMeter_inst/Counter_20
CTOF_DEL    ---     0.101      R7C17C.A1 to      R7C17C.F1 FrequencyMeter_inst/SLICE_70
ROUTE         1     0.000      R7C17C.F1 to R7C17C.DI1     FrequencyMeter_inst/n15 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_70:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i10  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16B.CLK to     R10C16B.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 (from Clock_c)
ROUTE         2     0.132     R10C16B.Q1 to R10C16B.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_10
CTOF_DEL    ---     0.101     R10C16B.A1 to     R10C16B.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96
ROUTE         1     0.000     R10C16B.F1 to R10C16B.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n10 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i14  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16D.CLK to     R10C16D.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 (from Clock_c)
ROUTE         2     0.132     R10C16D.Q1 to R10C16D.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_14
CTOF_DEL    ---     0.101     R10C16D.A1 to     R10C16D.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94
ROUTE         1     0.000     R10C16D.F1 to R10C16D.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n6 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i16  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i16  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/SLICE_72 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17A.CLK to      R7C17A.Q1 FrequencyMeter_inst/SLICE_72 (from Clock_c)
ROUTE         2     0.132      R7C17A.Q1 to R7C17A.A1      FrequencyMeter_inst/Counter_16
CTOF_DEL    ---     0.101      R7C17A.A1 to      R7C17A.F1 FrequencyMeter_inst/SLICE_72
ROUTE         1     0.000      R7C17A.F1 to R7C17A.DI1     FrequencyMeter_inst/n19 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i1  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15B.CLK to     R10C15B.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 (from Clock_c)
ROUTE         2     0.132     R10C15B.Q0 to R10C15B.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_1
CTOF_DEL    ---     0.101     R10C15B.A0 to     R10C15B.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100
ROUTE         1     0.000     R10C15B.F0 to R10C15B.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n19 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i12  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_74 to FrequencyMeter_inst/SLICE_74 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_74 to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16C.CLK to      R7C16C.Q1 FrequencyMeter_inst/SLICE_74 (from Clock_c)
ROUTE         2     0.132      R7C16C.Q1 to R7C16C.A1      FrequencyMeter_inst/Counter_12
CTOF_DEL    ---     0.101      R7C16C.A1 to      R7C16C.F1 FrequencyMeter_inst/SLICE_74
ROUTE         1     0.000      R7C16C.F1 to R7C16C.DI1     FrequencyMeter_inst/n23 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_74:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i17  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i17  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12B.CLK to      R2C12B.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 (from Clock_c)
ROUTE         2     0.132      R2C12B.Q0 to R2C12B.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_17
CTOF_DEL    ---     0.101      R2C12B.A0 to      R2C12B.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84
ROUTE         1     0.000      R2C12B.F0 to R2C12B.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n13 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i24  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i24  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/SLICE_68 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18A.CLK to      R7C18A.Q1 FrequencyMeter_inst/SLICE_68 (from Clock_c)
ROUTE         2     0.132      R7C18A.Q1 to R7C18A.A1      FrequencyMeter_inst/Counter_24
CTOF_DEL    ---     0.101      R7C18A.A1 to      R7C18A.F1 FrequencyMeter_inst/SLICE_68
ROUTE         1     0.000      R7C18A.F1 to R7C18A.DI1     FrequencyMeter_inst/n11 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i4  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13D.CLK to      R7C13D.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 (from Clock_c)
ROUTE         2     0.132      R7C13D.Q1 to R7C13D.A1      FrequencyMeter_inst/DoubleDabble_inst/Counter_4
CTOF_DEL    ---     0.101      R7C13D.A1 to      R7C13D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173
ROUTE         1     0.000      R7C13D.F1 to R7C13D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Counter_4_N_326_4 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i1  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10B.CLK to      R2C10B.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 (from Clock_c)
ROUTE         2     0.132      R2C10B.Q0 to R2C10B.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_1
CTOF_DEL    ---     0.101      R2C10B.A0 to      R2C10B.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92
ROUTE         1     0.000      R2C10B.F0 to R2C10B.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n29 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i4  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/SLICE_78 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15C.CLK to      R7C15C.Q1 FrequencyMeter_inst/SLICE_78 (from Clock_c)
ROUTE         2     0.132      R7C15C.Q1 to R7C15C.A1      FrequencyMeter_inst/Counter_4
CTOF_DEL    ---     0.101      R7C15C.A1 to      R7C15C.F1 FrequencyMeter_inst/SLICE_78
ROUTE         1     0.000      R7C15C.F1 to R7C15C.DI1     FrequencyMeter_inst/n31 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i5  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10D.CLK to      R2C10D.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 (from Clock_c)
ROUTE         2     0.132      R2C10D.Q0 to R2C10D.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_5
CTOF_DEL    ---     0.101      R2C10D.A0 to      R2C10D.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90
ROUTE         1     0.000      R2C10D.F0 to R2C10D.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n25 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i16  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i16  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12A.CLK to      R2C12A.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 (from Clock_c)
ROUTE         2     0.132      R2C12A.Q1 to R2C12A.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_16
CTOF_DEL    ---     0.101      R2C12A.A1 to      R2C12A.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85
ROUTE         1     0.000      R2C12A.F1 to R2C12A.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n14 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i9  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i9  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11B.CLK to      R2C11B.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 (from Clock_c)
ROUTE         2     0.132      R2C11B.Q0 to R2C11B.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_9
CTOF_DEL    ---     0.101      R2C11B.A0 to      R2C11B.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88
ROUTE         1     0.000      R2C11B.F0 to R2C11B.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n21 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/State_FSM_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i1  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay EncoderAmpl_inst/SLICE_121 to EncoderAmpl_inst/SLICE_121 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_121 to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14A.CLK to      R5C14A.Q0 EncoderAmpl_inst/SLICE_121 (from Clock_c)
ROUTE         3     0.132      R5C14A.Q0 to R5C14A.A0      EncoderAmpl_inst/n251
CTOF_DEL    ---     0.101      R5C14A.A0 to      R5C14A.F0 EncoderAmpl_inst/SLICE_121
ROUTE         1     0.000      R5C14A.F0 to R5C14A.DI0     EncoderAmpl_inst/n1980 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i13  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i13  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16D.CLK to     R10C16D.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94 (from Clock_c)
ROUTE         2     0.132     R10C16D.Q0 to R10C16D.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_13
CTOF_DEL    ---     0.101     R10C16D.A0 to     R10C16D.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94
ROUTE         1     0.000     R10C16D.F0 to R10C16D.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n7 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_94:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i3  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10C.CLK to      R2C10C.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91 (from Clock_c)
ROUTE         2     0.132      R2C10C.Q0 to R2C10C.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_3
CTOF_DEL    ---     0.101      R2C10C.A0 to      R2C10C.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91
ROUTE         1     0.000      R2C10C.F0 to R2C10C.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n27 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_91:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i23  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i23  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C13A.CLK to      R2C13A.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81 (from Clock_c)
ROUTE         2     0.132      R2C13A.Q0 to R2C13A.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_23
CTOF_DEL    ---     0.101      R2C13A.A0 to      R2C13A.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81
ROUTE         1     0.000      R2C13A.F0 to R2C13A.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n7 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_81:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i11  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i11  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_27 to DDS_inst/SLICE_27 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_27 to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9B.CLK to       R8C9B.Q1 DDS_inst/SLICE_27 (from Clock_c)
ROUTE         4     0.132       R8C9B.Q1 to R8C9B.A1       DDS_inst/Accumulator_11
CTOF_DEL    ---     0.101       R8C9B.A1 to       R8C9B.F1 DDS_inst/SLICE_27
ROUTE         1     0.000       R8C9B.F1 to R8C9B.DI1      DDS_inst/n74 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i22  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i22  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/SLICE_69 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17D.CLK to      R7C17D.Q1 FrequencyMeter_inst/SLICE_69 (from Clock_c)
ROUTE         2     0.132      R7C17D.Q1 to R7C17D.A1      FrequencyMeter_inst/Counter_22
CTOF_DEL    ---     0.101      R7C17D.A1 to      R7C17D.F1 FrequencyMeter_inst/SLICE_69
ROUTE         1     0.000      R7C17D.F1 to R7C17D.DI1     FrequencyMeter_inst/n13 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i25  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i25  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_67 to FrequencyMeter_inst/SLICE_67 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_67 to FrequencyMeter_inst/SLICE_67:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18B.CLK to      R7C18B.Q0 FrequencyMeter_inst/SLICE_67 (from Clock_c)
ROUTE         2     0.132      R7C18B.Q0 to R7C18B.A0      FrequencyMeter_inst/Counter_25
CTOF_DEL    ---     0.101      R7C18B.A0 to      R7C18B.F0 FrequencyMeter_inst/SLICE_67
ROUTE         1     0.000      R7C18B.F0 to R7C18B.DI0     FrequencyMeter_inst/n10 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_67:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_67:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i11  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16C.CLK to     R10C16C.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95 (from Clock_c)
ROUTE         2     0.132     R10C16C.Q0 to R10C16C.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_11
CTOF_DEL    ---     0.101     R10C16C.A0 to     R10C16C.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95
ROUTE         1     0.000     R10C16C.F0 to R10C16C.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n9 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_95:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i22  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i22  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12D.CLK to      R2C12D.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82 (from Clock_c)
ROUTE         2     0.132      R2C12D.Q1 to R2C12D.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_22
CTOF_DEL    ---     0.101      R2C12D.A1 to      R2C12D.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82
ROUTE         1     0.000      R2C12D.F1 to R2C12D.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n8 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_82:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i15  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i15  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12A.CLK to      R2C12A.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85 (from Clock_c)
ROUTE         2     0.132      R2C12A.Q0 to R2C12A.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_15
CTOF_DEL    ---     0.101      R2C12A.A0 to      R2C12A.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85
ROUTE         1     0.000      R2C12A.F0 to R2C12A.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n15 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_85:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i13  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i13  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_26 to DDS_inst/SLICE_26 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_26 to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9C.CLK to       R8C9C.Q1 DDS_inst/SLICE_26 (from Clock_c)
ROUTE         4     0.132       R8C9C.Q1 to R8C9C.A1       DDS_inst/Accumulator_13
CTOF_DEL    ---     0.101       R8C9C.A1 to       R8C9C.F1 DDS_inst/SLICE_26
ROUTE         1     0.000       R8C9C.F1 to R8C9C.DI1      DDS_inst/n72 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i12  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11C.CLK to      R2C11C.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 (from Clock_c)
ROUTE         2     0.132      R2C11C.Q1 to R2C11C.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_12
CTOF_DEL    ---     0.101      R2C11C.A1 to      R2C11C.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87
ROUTE         1     0.000      R2C11C.F1 to R2C11C.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n18 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16A.CLK to     R10C16A.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 (from Clock_c)
ROUTE         2     0.132     R10C16A.Q0 to R10C16A.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_7
CTOF_DEL    ---     0.101     R10C16A.A0 to     R10C16A.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97
ROUTE         1     0.000     R10C16A.F0 to R10C16A.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n13 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i19  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i19  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12C.CLK to      R2C12C.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 (from Clock_c)
ROUTE         2     0.132      R2C12C.Q0 to R2C12C.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_19
CTOF_DEL    ---     0.101      R2C12C.A0 to      R2C12C.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83
ROUTE         1     0.000      R2C12C.F0 to R2C12C.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n11 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i1  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/SLICE_79 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15B.CLK to      R7C15B.Q0 FrequencyMeter_inst/SLICE_79 (from Clock_c)
ROUTE         2     0.132      R7C15B.Q0 to R7C15B.A0      FrequencyMeter_inst/Counter_1
CTOF_DEL    ---     0.101      R7C15B.A0 to      R7C15B.F0 FrequencyMeter_inst/SLICE_79
ROUTE         1     0.000      R7C15B.F0 to R7C15B.DI0     FrequencyMeter_inst/n34 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i5  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/SLICE_77 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15D.CLK to      R7C15D.Q0 FrequencyMeter_inst/SLICE_77 (from Clock_c)
ROUTE         2     0.132      R7C15D.Q0 to R7C15D.A0      FrequencyMeter_inst/Counter_5
CTOF_DEL    ---     0.101      R7C15D.A0 to      R7C15D.F0 FrequencyMeter_inst/SLICE_77
ROUTE         1     0.000      R7C15D.F0 to R7C15D.DI0     FrequencyMeter_inst/n30 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i9  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i9  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/SLICE_75 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16B.CLK to      R7C16B.Q0 FrequencyMeter_inst/SLICE_75 (from Clock_c)
ROUTE         2     0.132      R7C16B.Q0 to R7C16B.A0      FrequencyMeter_inst/Counter_9
CTOF_DEL    ---     0.101      R7C16B.A0 to      R7C16B.F0 FrequencyMeter_inst/SLICE_75
ROUTE         1     0.000      R7C16B.F0 to R7C16B.DI0     FrequencyMeter_inst/n26 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i13  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i13  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/SLICE_73 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16D.CLK to      R7C16D.Q0 FrequencyMeter_inst/SLICE_73 (from Clock_c)
ROUTE         2     0.132      R7C16D.Q0 to R7C16D.A0      FrequencyMeter_inst/Counter_13
CTOF_DEL    ---     0.101      R7C16D.A0 to      R7C16D.F0 FrequencyMeter_inst/SLICE_73
ROUTE         1     0.000      R7C16D.F0 to R7C16D.DI0     FrequencyMeter_inst/n22 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i17  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i17  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_71 to FrequencyMeter_inst/SLICE_71 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_71 to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17B.CLK to      R7C17B.Q0 FrequencyMeter_inst/SLICE_71 (from Clock_c)
ROUTE         2     0.132      R7C17B.Q0 to R7C17B.A0      FrequencyMeter_inst/Counter_17
CTOF_DEL    ---     0.101      R7C17B.A0 to      R7C17B.F0 FrequencyMeter_inst/SLICE_71
ROUTE         1     0.000      R7C17B.F0 to R7C17B.DI0     FrequencyMeter_inst/n18 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i21  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i21  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/SLICE_69 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17D.CLK to      R7C17D.Q0 FrequencyMeter_inst/SLICE_69 (from Clock_c)
ROUTE         2     0.132      R7C17D.Q0 to R7C17D.A0      FrequencyMeter_inst/Counter_21
CTOF_DEL    ---     0.101      R7C17D.A0 to      R7C17D.F0 FrequencyMeter_inst/SLICE_69
ROUTE         1     0.000      R7C17D.F0 to R7C17D.DI0     FrequencyMeter_inst/n14 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i14  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/SLICE_73 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16D.CLK to      R7C16D.Q1 FrequencyMeter_inst/SLICE_73 (from Clock_c)
ROUTE         2     0.132      R7C16D.Q1 to R7C16D.A1      FrequencyMeter_inst/Counter_14
CTOF_DEL    ---     0.101      R7C16D.A1 to      R7C16D.F1 FrequencyMeter_inst/SLICE_73
ROUTE         1     0.000      R7C16D.F1 to R7C16D.DI1     FrequencyMeter_inst/n21 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10B.CLK to      R2C10B.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92 (from Clock_c)
ROUTE         2     0.132      R2C10B.Q1 to R2C10B.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_2
CTOF_DEL    ---     0.101      R2C10B.A1 to      R2C10B.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92
ROUTE         1     0.000      R2C10B.F1 to R2C10B.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n28 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_92:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i6  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C10D.CLK to      R2C10D.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90 (from Clock_c)
ROUTE         2     0.132      R2C10D.Q1 to R2C10D.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_6
CTOF_DEL    ---     0.101      R2C10D.A1 to      R2C10D.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90
ROUTE         1     0.000      R2C10D.F1 to R2C10D.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n24 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_90:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i8  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16A.CLK to     R10C16A.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97 (from Clock_c)
ROUTE         2     0.132     R10C16A.Q1 to R10C16A.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_8
CTOF_DEL    ---     0.101     R10C16A.A1 to     R10C16A.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97
ROUTE         1     0.000     R10C16A.F1 to R10C16A.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n12 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_97:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16A.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i20  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i20  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12C.CLK to      R2C12C.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83 (from Clock_c)
ROUTE         2     0.132      R2C12C.Q1 to R2C12C.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_20
CTOF_DEL    ---     0.101      R2C12C.A1 to      R2C12C.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83
ROUTE         1     0.000      R2C12C.F1 to R2C12C.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n10 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_83:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/SLICE_79 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15B.CLK to      R7C15B.Q1 FrequencyMeter_inst/SLICE_79 (from Clock_c)
ROUTE         2     0.132      R7C15B.Q1 to R7C15B.A1      FrequencyMeter_inst/Counter_2
CTOF_DEL    ---     0.101      R7C15B.A1 to      R7C15B.F1 FrequencyMeter_inst/SLICE_79
ROUTE         1     0.000      R7C15B.F1 to R7C15B.DI1     FrequencyMeter_inst/n33 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i6  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/SLICE_77 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15D.CLK to      R7C15D.Q1 FrequencyMeter_inst/SLICE_77 (from Clock_c)
ROUTE         2     0.132      R7C15D.Q1 to R7C15D.A1      FrequencyMeter_inst/Counter_6
CTOF_DEL    ---     0.101      R7C15D.A1 to      R7C15D.F1 FrequencyMeter_inst/SLICE_77
ROUTE         1     0.000      R7C15D.F1 to R7C15D.DI1     FrequencyMeter_inst/n29 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i10  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/SLICE_75 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16B.CLK to      R7C16B.Q1 FrequencyMeter_inst/SLICE_75 (from Clock_c)
ROUTE         2     0.132      R7C16B.Q1 to R7C16B.A1      FrequencyMeter_inst/Counter_10
CTOF_DEL    ---     0.101      R7C16B.A1 to      R7C16B.F1 FrequencyMeter_inst/SLICE_75
ROUTE         1     0.000      R7C16B.F1 to R7C16B.DI1     FrequencyMeter_inst/n25 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i4  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15C.CLK to     R10C15C.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99 (from Clock_c)
ROUTE         2     0.132     R10C15C.Q1 to R10C15C.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_4
CTOF_DEL    ---     0.101     R10C15C.A1 to     R10C15C.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99
ROUTE         1     0.000     R10C15C.F1 to R10C15C.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n16 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_99:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15C.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i14  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11D.CLK to      R2C11D.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 (from Clock_c)
ROUTE         2     0.132      R2C11D.Q1 to R2C11D.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_14
CTOF_DEL    ---     0.101      R2C11D.A1 to      R2C11D.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86
ROUTE         1     0.000      R2C11D.F1 to R2C11D.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n16 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i10  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11B.CLK to      R2C11B.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88 (from Clock_c)
ROUTE         2     0.132      R2C11B.Q1 to R2C11B.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_10
CTOF_DEL    ---     0.101      R2C11B.A1 to      R2C11B.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88
ROUTE         1     0.000      R2C11B.F1 to R2C11B.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n20 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_88:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i9  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i9  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_28 to DDS_inst/SLICE_28 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_28 to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9A.CLK to       R8C9A.Q1 DDS_inst/SLICE_28 (from Clock_c)
ROUTE         4     0.132       R8C9A.Q1 to R8C9A.A1       DDS_inst/Accumulator_9
CTOF_DEL    ---     0.101       R8C9A.A1 to       R8C9A.F1 DDS_inst/SLICE_28
ROUTE         1     0.000       R8C9A.F1 to R8C9A.DI1      DDS_inst/n76 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i7  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_29 to DDS_inst/SLICE_29 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_29 to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C8D.CLK to       R8C8D.Q1 DDS_inst/SLICE_29 (from Clock_c)
ROUTE         4     0.132       R8C8D.Q1 to R8C8D.A1       DDS_inst/Accumulator_7
CTOF_DEL    ---     0.101       R8C8D.A1 to       R8C8D.F1 DDS_inst/SLICE_29
ROUTE         1     0.000       R8C8D.F1 to R8C8D.DI1      DDS_inst/n78 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_29:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i0  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i0  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_110 to DDS_inst/SLICE_110 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_110 to DDS_inst/SLICE_110:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C7A.CLK to       R8C7A.Q0 DDS_inst/SLICE_110 (from Clock_c)
ROUTE         2     0.132       R8C7A.Q0 to R8C7A.A0       DDS_inst/n16
CTOF_DEL    ---     0.101       R8C7A.A0 to       R8C7A.F0 DDS_inst/SLICE_110
ROUTE         1     0.000       R8C7A.F0 to R8C7A.DI0      DDS_inst/n85 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_110:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C7A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_110:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C7A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i12  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i12  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay DDS_inst/SLICE_26 to DDS_inst/SLICE_26 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path DDS_inst/SLICE_26 to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9C.CLK to       R8C9C.Q0 DDS_inst/SLICE_26 (from Clock_c)
ROUTE         4     0.132       R8C9C.Q0 to R8C9C.A0       DDS_inst/Accumulator_12
CTOF_DEL    ---     0.101       R8C9C.A0 to       R8C9C.F0 DDS_inst/SLICE_26
ROUTE         1     0.000       R8C9C.F0 to R8C9C.DI0      DDS_inst/n73 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_26:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i11  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11C.CLK to      R2C11C.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87 (from Clock_c)
ROUTE         2     0.132      R2C11C.Q0 to R2C11C.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_11
CTOF_DEL    ---     0.101      R2C11C.A0 to      R2C11C.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87
ROUTE         1     0.000      R2C11C.F0 to R2C11C.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n19 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_87:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C15B.CLK to     R10C15B.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100 (from Clock_c)
ROUTE         2     0.132     R10C15B.Q1 to R10C15B.A1     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_2
CTOF_DEL    ---     0.101     R10C15B.A1 to     R10C15B.F1 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100
ROUTE         1     0.000     R10C15B.F1 to R10C15B.DI1    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n18 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_100:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C15B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i9  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_i9  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C16B.CLK to     R10C16B.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96 (from Clock_c)
ROUTE         2     0.132     R10C16B.Q0 to R10C16B.A0     FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/Counter_9
CTOF_DEL    ---     0.101     R10C16B.A0 to     R10C16B.F0 FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96
ROUTE         1     0.000     R10C16B.F0 to R10C16B.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/n11 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/StrobeGenerator0/SLICE_96:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C16B.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i18  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i18  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C12B.CLK to      R2C12B.Q1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84 (from Clock_c)
ROUTE         2     0.132      R2C12B.Q1 to R2C12B.A1      FrequencyMeter_inst/StrobeGenerator_inst/Counter_18
CTOF_DEL    ---     0.101      R2C12B.A1 to      R2C12B.F1 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84
ROUTE         1     0.000      R2C12B.F1 to R2C12B.DI1     FrequencyMeter_inst/StrobeGenerator_inst/n12 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_84:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C12B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/StrobeGenerator_inst/Counter_i13  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/StrobeGenerator_inst/Counter_i13  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R2C11D.CLK to      R2C11D.Q0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86 (from Clock_c)
ROUTE         2     0.132      R2C11D.Q0 to R2C11D.A0      FrequencyMeter_inst/StrobeGenerator_inst/Counter_13
CTOF_DEL    ---     0.101      R2C11D.A0 to      R2C11D.F0 FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86
ROUTE         1     0.000      R2C11D.F0 to R2C11D.DI0     FrequencyMeter_inst/StrobeGenerator_inst/n17 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/StrobeGenerator_inst/SLICE_86:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R2C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i18  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Counter__i18  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay FrequencyMeter_inst/SLICE_71 to FrequencyMeter_inst/SLICE_71 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_71 to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17B.CLK to      R7C17B.Q1 FrequencyMeter_inst/SLICE_71 (from Clock_c)
ROUTE         2     0.132      R7C17B.Q1 to R7C17B.A1      FrequencyMeter_inst/Counter_18
CTOF_DEL    ---     0.101      R7C17B.A1 to      R7C17B.F1 FrequencyMeter_inst/SLICE_71
ROUTE         1     0.000      R7C17B.F1 to R7C17B.DI1     FrequencyMeter_inst/n17 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_71:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i2  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_102 to SLICE_102 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_102 to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q0 SLICE_102 (from Clock_c)
ROUTE        10     0.132      R5C11C.Q0 to R5C11C.A0      Amplitude_2
CTOF_DEL    ---     0.101      R5C11C.A0 to      R5C11C.F0 SLICE_102
ROUTE         1     0.000      R5C11C.F0 to R5C11C.DI0     Amplitude_7_N_11_2 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i3  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i3  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_102 to SLICE_102 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_102 to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q1 SLICE_102 (from Clock_c)
ROUTE         9     0.132      R5C11C.Q1 to R5C11C.A1      Amplitude_3
CTOF_DEL    ---     0.101      R5C11C.A1 to      R5C11C.F1 SLICE_102
ROUTE         1     0.000      R5C11C.F1 to R5C11C.DI1     Amplitude_7_N_11_3 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_102:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i6  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_59 to SLICE_59 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_59 to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C9A.CLK to       R9C9A.Q0 SLICE_59 (from Clock_c)
ROUTE         2     0.132       R9C9A.Q0 to R9C9A.A0       TuningWord_6
CTOF_DEL    ---     0.101       R9C9A.A0 to       R9C9A.F0 SLICE_59
ROUTE         1     0.000       R9C9A.F0 to R9C9A.DI0      TuningWord_7_N_1_6 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i7  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_59 to SLICE_59 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_59 to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C9A.CLK to       R9C9A.Q1 SLICE_59 (from Clock_c)
ROUTE         2     0.132       R9C9A.Q1 to R9C9A.A1       TuningWord_7
CTOF_DEL    ---     0.101       R9C9A.A1 to       R9C9A.F1 SLICE_59
ROUTE         1     0.000       R9C9A.F1 to R9C9A.DI1      TuningWord_7_N_1_7 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_59:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i4  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i4  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_60 to SLICE_60 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_60 to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8D.CLK to       R9C8D.Q0 SLICE_60 (from Clock_c)
ROUTE         2     0.132       R9C8D.Q0 to R9C8D.A0       TuningWord_4
CTOF_DEL    ---     0.101       R9C8D.A0 to       R9C8D.F0 SLICE_60
ROUTE         1     0.000       R9C8D.F0 to R9C8D.DI0      TuningWord_7_N_1_4 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i5  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i5  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_60 to SLICE_60 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_60 to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8D.CLK to       R9C8D.Q1 SLICE_60 (from Clock_c)
ROUTE         2     0.132       R9C8D.Q1 to R9C8D.A1       TuningWord_5
CTOF_DEL    ---     0.101       R9C8D.A1 to       R9C8D.F1 SLICE_60
ROUTE         1     0.000       R9C8D.F1 to R9C8D.DI1      TuningWord_7_N_1_5 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_60:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i2  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i2  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_61 to SLICE_61 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_61 to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8C.CLK to       R9C8C.Q0 SLICE_61 (from Clock_c)
ROUTE         2     0.132       R9C8C.Q0 to R9C8C.A0       TuningWord_2
CTOF_DEL    ---     0.101       R9C8C.A0 to       R9C8C.F0 SLICE_61
ROUTE         1     0.000       R9C8C.F0 to R9C8C.DI0      TuningWord_7_N_1_2 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i3  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i3  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_61 to SLICE_61 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_61 to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8C.CLK to       R9C8C.Q1 SLICE_61 (from Clock_c)
ROUTE         2     0.132       R9C8C.Q1 to R9C8C.A1       TuningWord_3
CTOF_DEL    ---     0.101       R9C8C.A1 to       R9C8C.F1 SLICE_61
ROUTE         1     0.000       R9C8C.F1 to R9C8C.DI1      TuningWord_7_N_1_3 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_61:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8C.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i1  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i1  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_62 to SLICE_62 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_62 to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8B.CLK to       R9C8B.Q1 SLICE_62 (from Clock_c)
ROUTE         2     0.132       R9C8B.Q1 to R9C8B.A1       TuningWord_1
CTOF_DEL    ---     0.101       R9C8B.A1 to       R9C8B.F1 SLICE_62
ROUTE         1     0.000       R9C8B.F1 to R9C8B.DI1      TuningWord_7_N_1_1 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i5  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i5  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_64 to SLICE_64 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_64 to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11D.CLK to      R5C11D.Q1 SLICE_64 (from Clock_c)
ROUTE         9     0.132      R5C11D.Q1 to R5C11D.A1      Amplitude_5
CTOF_DEL    ---     0.101      R5C11D.A1 to      R5C11D.F1 SLICE_64
ROUTE         1     0.000      R5C11D.F1 to R5C11D.DI1     Amplitude_7_N_11_5 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i6  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i6  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_65 to SLICE_65 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_65 to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C12A.CLK to      R5C12A.Q0 SLICE_65 (from Clock_c)
ROUTE        10     0.132      R5C12A.Q0 to R5C12A.A0      Amplitude_6
CTOF_DEL    ---     0.101      R5C12A.A0 to      R5C12A.F0 SLICE_65
ROUTE         1     0.000      R5C12A.F0 to R5C12A.DI0     Amplitude_7_N_11_6 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.379ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i7  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i7  (to Clock_c +)

   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.

 Constraint Details:

      0.366ns physical path delay SLICE_65 to SLICE_65 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.379ns

 Physical Path Details:

      Data path SLICE_65 to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C12A.CLK to      R5C12A.Q1 SLICE_65 (from Clock_c)
ROUTE         9     0.132      R5C12A.Q1 to R5C12A.A1      Amplitude_7
CTOF_DEL    ---     0.101      R5C12A.A1 to      R5C12A.F1 SLICE_65
ROUTE         1     0.000      R5C12A.F1 to R5C12A.DI1     Amplitude_7_N_11_7 (to Clock_c)
                  --------
                    0.366   (63.9% logic, 36.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_65:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i31  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i31  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15C.CLK to      R9C15C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 (from Clock_c)
ROUTE         4     0.133      R9C15C.Q0 to R9C15C.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_31
CTOF_DEL    ---     0.101      R9C15C.A0 to      R9C15C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_156
ROUTE         1     0.000      R9C15C.F0 to R9C15C.DI0     FrequencyMeter_inst/DoubleDabble_inst/n142 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i4  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 (from Clock_c)
ROUTE         6     0.133      R8C14B.Q0 to R8C14B.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_4
CTOF_DEL    ---     0.101      R8C14B.A0 to      R8C14B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142
ROUTE         1     0.000      R8C14B.F0 to R8C14B.DI0     FrequencyMeter_inst/DoubleDabble_inst/n169 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i5  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 (from Clock_c)
ROUTE         6     0.133      R8C14B.Q1 to R8C14B.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_5
CTOF_DEL    ---     0.101      R8C14B.A1 to      R8C14B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142
ROUTE         1     0.000      R8C14B.F1 to R8C14B.DI1     FrequencyMeter_inst/DoubleDabble_inst/n168 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i11  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C16B.CLK to      R8C16B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 (from Clock_c)
ROUTE         1     0.133      R8C16B.Q1 to R8C16A.D0      FrequencyMeter_inst/DoubleDabble_inst/Binary_10
CTOF_DEL    ---     0.101      R8C16A.D0 to      R8C16A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_163
ROUTE         1     0.000      R8C16A.F0 to R8C16A.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_11 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i14  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C10A.CLK to      R9C10A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_147 (from Clock_c)
ROUTE         5     0.133      R9C10A.Q0 to R9C10A.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_14
CTOF_DEL    ---     0.101      R9C10A.A0 to      R9C10A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_147
ROUTE         1     0.000      R9C10A.F0 to R9C10A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n159 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_147:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i8  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i8  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay DDS_inst/SLICE_28 to DDS_inst/SLICE_28 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path DDS_inst/SLICE_28 to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9A.CLK to       R8C9A.Q0 DDS_inst/SLICE_28 (from Clock_c)
ROUTE         4     0.133       R8C9A.Q0 to R8C9A.A0       DDS_inst/Accumulator_8
CTOF_DEL    ---     0.101       R8C9A.A0 to       R8C9A.F0 DDS_inst/SLICE_28
ROUTE         1     0.000       R8C9A.F0 to R8C9A.DI0      DDS_inst/n77 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_28:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9A.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i2  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13B.CLK to      R7C13B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 (from Clock_c)
ROUTE         4     0.133      R7C13B.Q1 to R7C13B.A1      FrequencyMeter_inst/DoubleDabble_inst/Counter_2
CTOF_DEL    ---     0.101      R7C13B.A1 to      R7C13B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_172
ROUTE         1     0.000      R7C13B.F1 to R7C13B.DI1     FrequencyMeter_inst/DoubleDabble_inst/n1215 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/State_FSM_i3  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i3  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay EncoderFreq_inst/SLICE_125 to EncoderFreq_inst/SLICE_125 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_125 to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C15B.CLK to      R5C15B.Q0 EncoderFreq_inst/SLICE_125 (from Clock_c)
ROUTE         6     0.133      R5C15B.Q0 to R5C15B.A0      EncoderFreq_inst/n191
CTOF_DEL    ---     0.101      R5C15B.A0 to      R5C15B.F0 EncoderFreq_inst/SLICE_125
ROUTE         1     0.000      R5C15B.F0 to R5C15B.DI0     EncoderFreq_inst/n1270 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i17  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i17  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13B.CLK to      R8C13B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 (from Clock_c)
ROUTE         6     0.133      R8C13B.Q1 to R8C13B.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_17
CTOF_DEL    ---     0.101      R8C13B.A1 to      R8C13B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_148
ROUTE         1     0.000      R8C13B.F1 to R8C13B.DI1     FrequencyMeter_inst/DoubleDabble_inst/n156 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i20  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i20  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_150 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_150 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13A.CLK to      R9C13A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_150 (from Clock_c)
ROUTE         6     0.133      R9C13A.Q0 to R9C13A.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_20
CTOF_DEL    ---     0.101      R9C13A.A0 to      R9C13A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_150
ROUTE         1     0.000      R9C13A.F0 to R9C13A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n153 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i14  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i14  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay DDS_inst/SLICE_10 to DDS_inst/SLICE_10 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path DDS_inst/SLICE_10 to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9D.CLK to       R8C9D.Q0 DDS_inst/SLICE_10 (from Clock_c)
ROUTE         4     0.133       R8C9D.Q0 to R8C9D.A0       DDS_inst/Accumulator_14
CTOF_DEL    ---     0.101       R8C9D.A0 to       R8C9D.F0 DDS_inst/SLICE_10
ROUTE         1     0.000       R8C9D.F0 to R8C9D.DI0      DDS_inst/n71 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i3  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13D.CLK to      R7C13D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 (from Clock_c)
ROUTE         3     0.133      R7C13D.Q0 to R7C13D.A0      FrequencyMeter_inst/DoubleDabble_inst/Counter_3
CTOF_DEL    ---     0.101      R7C13D.A0 to      R7C13D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173
ROUTE         1     0.000      R7C13D.F0 to R7C13D.DI0     FrequencyMeter_inst/DoubleDabble_inst/Counter_4_N_326_3 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i26  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i26  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_153 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_153 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_153 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_153:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14A.CLK to      R8C14A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_153 (from Clock_c)
ROUTE         5     0.133      R8C14A.Q1 to R8C14A.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_26
CTOF_DEL    ---     0.101      R8C14A.A1 to      R8C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_153
ROUTE         1     0.000      R8C14A.F1 to R8C14A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n147 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_153:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_153:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i10  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i10  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay DDS_inst/SLICE_27 to DDS_inst/SLICE_27 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path DDS_inst/SLICE_27 to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9B.CLK to       R8C9B.Q0 DDS_inst/SLICE_27 (from Clock_c)
ROUTE         4     0.133       R8C9B.Q0 to R8C9B.A0       DDS_inst/Accumulator_10
CTOF_DEL    ---     0.101       R8C9B.A0 to       R8C9B.F0 DDS_inst/SLICE_27
ROUTE         1     0.000       R8C9B.F0 to R8C9B.DI0      DDS_inst/n75 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_27:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i16  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i16  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13B.CLK to      R8C13B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_148 (from Clock_c)
ROUTE         6     0.133      R8C13B.Q0 to R8C13B.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_16
CTOF_DEL    ---     0.101      R8C13B.A0 to      R8C13B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_148
ROUTE         1     0.000      R8C13B.F0 to R8C13B.DI0     FrequencyMeter_inst/DoubleDabble_inst/n157 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_148:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i11  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 (from Clock_c)
ROUTE         5     0.133      R8C12A.Q1 to R8C12A.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_11
CTOF_DEL    ---     0.101      R8C12A.A1 to      R8C12A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145
ROUTE         1     0.000      R8C12A.F1 to R8C12A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n162 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i10  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C12A.CLK to      R8C12A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145 (from Clock_c)
ROUTE         5     0.133      R8C12A.Q0 to R8C12A.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_10
CTOF_DEL    ---     0.101      R8C12A.A0 to      R8C12A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_145
ROUTE         1     0.000      R8C12A.F0 to R8C12A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n163 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_145:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i9  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 (from Clock_c)
ROUTE         1     0.133      R8C16D.Q1 to R8C16B.D0      FrequencyMeter_inst/DoubleDabble_inst/Binary_8
CTOF_DEL    ---     0.101      R8C16B.D0 to      R8C16B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_162
ROUTE         1     0.000      R8C16B.F0 to R8C16B.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_9 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i21  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i22  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18C.CLK to      R7C18C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 (from Clock_c)
ROUTE         1     0.133      R7C18C.Q0 to R7C18C.D1      FrequencyMeter_inst/DoubleDabble_inst/Binary_21
CTOF_DEL    ---     0.101      R7C18C.D1 to      R7C18C.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_168
ROUTE         1     0.000      R7C18C.F1 to R7C18C.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_22 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i21  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i21  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13B.CLK to      R9C13B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 (from Clock_c)
ROUTE         6     0.133      R9C13B.Q0 to R9C13B.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_21
CTOF_DEL    ---     0.101      R9C13B.A0 to      R9C13B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_151
ROUTE         1     0.000      R9C13B.F0 to R9C13B.DI0     FrequencyMeter_inst/DoubleDabble_inst/n152 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i3  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11D.CLK to      R7C11D.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 (from Clock_c)
ROUTE         5     0.133      R7C11D.Q1 to R7C11D.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_3
CTOF_DEL    ---     0.101      R7C11D.A1 to      R7C11D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141
ROUTE         1     0.000      R7C11D.F1 to R7C11D.DI1     FrequencyMeter_inst/DoubleDabble_inst/n170 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i0  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_140:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11C.CLK to      R7C11C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_140 (from Clock_c)
ROUTE         6     0.133      R7C11C.Q0 to R7C11C.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_0
CTOF_DEL    ---     0.101      R7C11C.A0 to      R7C11C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_140
ROUTE         1     0.000      R7C11C.F0 to R7C11C.DI0     FrequencyMeter_inst/DoubleDabble_inst/n173 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_140:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_140:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              DDS_inst/Accumulator_334__i15  (from Clock_c +)
   Destination:    FF         Data in        DDS_inst/Accumulator_334__i15  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay DDS_inst/SLICE_10 to DDS_inst/SLICE_10 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path DDS_inst/SLICE_10 to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R8C9D.CLK to       R8C9D.Q1 DDS_inst/SLICE_10 (from Clock_c)
ROUTE         4     0.133       R8C9D.Q1 to R8C9D.A1       DDS_inst/Accumulator_15
CTOF_DEL    ---     0.101       R8C9D.A1 to       R8C9D.F1 DDS_inst/SLICE_10
ROUTE         1     0.000       R8C9D.F1 to R8C9D.DI1      DDS_inst/n70 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to DDS_inst/SLICE_10:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C9D.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i1  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i1  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay SLICE_58 to SLICE_58 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path SLICE_58 to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q1 SLICE_58 (from Clock_c)
ROUTE         9     0.133      R5C11B.Q1 to R5C11B.A1      Amplitude_1
CTOF_DEL    ---     0.101      R5C11B.A1 to      R5C11B.F1 SLICE_58
ROUTE         1     0.000      R5C11B.F1 to R5C11B.DI1     Amplitude_7_N_11_1 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.380ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i4  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i4  (to Clock_c +)

   Delay:               0.367ns  (63.8% logic, 36.2% route), 2 logic levels.

 Constraint Details:

      0.367ns physical path delay SLICE_64 to SLICE_64 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.380ns

 Physical Path Details:

      Data path SLICE_64 to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11D.CLK to      R5C11D.Q0 SLICE_64 (from Clock_c)
ROUTE        10     0.133      R5C11D.Q0 to R5C11D.A0      Amplitude_4
CTOF_DEL    ---     0.101      R5C11D.A0 to      R5C11D.F0 SLICE_64
ROUTE         1     0.000      R5C11D.F0 to R5C11D.DI0     Amplitude_7_N_11_4 (to Clock_c)
                  --------
                    0.367   (63.8% logic, 36.2% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_64:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i0  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i0  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_171 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_171 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_171 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_171:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13C.CLK to      R7C13C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_171 (from Clock_c)
ROUTE         6     0.134      R7C13C.Q0 to R7C13C.A0      FrequencyMeter_inst/DoubleDabble_inst/Counter_0
CTOF_DEL    ---     0.101      R7C13C.A0 to      R7C13C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_171
ROUTE         1     0.000      R7C13C.F0 to R7C13C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Counter_4_N_326_0 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_171:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_171:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i28  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i28  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 (from Clock_c)
ROUTE         6     0.134      R9C14C.Q1 to R9C14C.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_28
CTOF_DEL    ---     0.101      R9C14C.A1 to      R9C14C.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154
ROUTE         1     0.000      R9C14C.F1 to R9C14C.DI1     FrequencyMeter_inst/DoubleDabble_inst/n145 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i19  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i19  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13A.CLK to      R8C13A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 (from Clock_c)
ROUTE         5     0.134      R8C13A.Q1 to R8C13A.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_19
CTOF_DEL    ---     0.101      R8C13A.A1 to      R8C13A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149
ROUTE         1     0.000      R8C13A.F1 to R8C13A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n154 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i1  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13B.CLK to      R7C13B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 (from Clock_c)
ROUTE         5     0.134      R7C13B.Q0 to R7C13B.A0      FrequencyMeter_inst/DoubleDabble_inst/Counter_1
CTOF_DEL    ---     0.101      R7C13B.A0 to      R7C13B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_172
ROUTE         1     0.000      R7C13B.F0 to R7C13B.DI0     FrequencyMeter_inst/DoubleDabble_inst/n1217 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i2  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11D.CLK to      R7C11D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 (from Clock_c)
ROUTE         5     0.134      R7C11D.Q0 to R7C11D.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_2
CTOF_DEL    ---     0.101      R7C11D.A0 to      R7C11D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141
ROUTE         1     0.000      R7C11D.F0 to R7C11D.DI0     FrequencyMeter_inst/DoubleDabble_inst/n171 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i18  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i18  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13A.CLK to      R8C13A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 (from Clock_c)
ROUTE         5     0.134      R8C13A.Q0 to R8C13A.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_18
CTOF_DEL    ---     0.101      R8C13A.A0 to      R8C13A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149
ROUTE         1     0.000      R8C13A.F0 to R8C13A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n155 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i29  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i29  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15A.CLK to      R9C15A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 (from Clock_c)
ROUTE         6     0.134      R9C15A.Q0 to R9C15A.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_29
CTOF_DEL    ---     0.101      R9C15A.A0 to      R9C15A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_155
ROUTE         1     0.000      R9C15A.F0 to R9C15A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n144 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.381ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i8  (to Clock_c +)

   Delay:               0.368ns  (63.6% logic, 36.4% route), 2 logic levels.

 Constraint Details:

      0.368ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_144 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_144 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.381ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_144 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_144:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C12D.CLK to      R7C12D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_144 (from Clock_c)
ROUTE         6     0.134      R7C12D.Q0 to R7C12D.A0      FrequencyMeter_inst/DoubleDabble_inst/BCD_8
CTOF_DEL    ---     0.101      R7C12D.A0 to      R7C12D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_144
ROUTE         1     0.000      R7C12D.F0 to R7C12D.DI0     FrequencyMeter_inst/DoubleDabble_inst/n165 (to Clock_c)
                  --------
                    0.368   (63.6% logic, 36.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_144:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_144:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C12D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.382ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i22  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i22  (to Clock_c +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13B.CLK to      R9C13B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 (from Clock_c)
ROUTE         5     0.135      R9C13B.Q1 to R9C13B.A1      FrequencyMeter_inst/DoubleDabble_inst/BCD_22
CTOF_DEL    ---     0.101      R9C13B.A1 to      R9C13B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_151
ROUTE         1     0.000      R9C13B.F1 to R9C13B.DI1     FrequencyMeter_inst/DoubleDabble_inst/n151 (to Clock_c)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.382ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i1  (to Clock_c +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C17C.CLK to      R9C17C.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 (from Clock_c)
ROUTE        30     0.135      R9C17C.Q0 to R9C17C.A0      TempData_3_N_450_2
CTOF_DEL    ---     0.101      R9C17C.A0 to      R9C17C.F0 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182
ROUTE         1     0.000      R9C17C.F0 to R9C17C.DI0     FrequencyMeter_inst/DisplayMultiplex_inst/n2211 (to Clock_c)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.382ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/State_95  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/State_95  (to Clock_c +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_174 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_174 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C14B.CLK to      R7C14B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_174 (from Clock_c)
ROUTE        39     0.135      R7C14B.Q0 to R7C14B.A0      FrequencyMeter_inst/DoubleDabble_inst/State
CTOF_DEL    ---     0.101      R7C14B.A0 to      R7C14B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_174
ROUTE         1     0.000      R7C14B.F0 to R7C14B.DI0     FrequencyMeter_inst/DoubleDabble_inst/State_N_434 (to Clock_c)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.382ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i3  (to Clock_c +)

   Delay:               0.369ns  (63.4% logic, 36.6% route), 2 logic levels.

 Constraint Details:

      0.369ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.382ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    R10C17D.CLK to     R10C17D.Q0 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183 (from Clock_c)
ROUTE        24     0.135     R10C17D.Q0 to R10C17D.A0     TempData_3_N_450_4
CTOF_DEL    ---     0.101     R10C17D.A0 to     R10C17D.F0 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183
ROUTE         1     0.000     R10C17D.F0 to R10C17D.DI0    FrequencyMeter_inst/DisplayMultiplex_inst/n18 (to Clock_c)
                  --------
                    0.369   (63.4% logic, 36.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C17D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_183:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R10C17D.CLK    Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i8  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C16D.CLK to      R8C16D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 (from Clock_c)
ROUTE         1     0.136      R8C16D.Q0 to R8C16D.C1      FrequencyMeter_inst/DoubleDabble_inst/Binary_7
CTOF_DEL    ---     0.101      R8C16D.C1 to      R8C16D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_161
ROUTE         1     0.000      R8C16D.F1 to R8C16D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_8 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DisplayMultiplex_inst/Selector_335__i2  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C17C.CLK to      R9C17C.Q1 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182 (from Clock_c)
ROUTE        18     0.136      R9C17C.Q1 to R9C17C.D1      TempData_3_N_450_3
CTOF_DEL    ---     0.101      R9C17C.D1 to      R9C17C.F1 FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182
ROUTE         1     0.000      R9C17C.F1 to R9C17C.DI1     FrequencyMeter_inst/DisplayMultiplex_inst/n19 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DisplayMultiplex_inst/SLICE_182:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C17C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i5  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_159 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_159 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C15B.CLK to      R8C15B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_159 (from Clock_c)
ROUTE         1     0.136      R8C15B.Q1 to R8C15C.C0      FrequencyMeter_inst/DoubleDabble_inst/Binary_4
CTOF_DEL    ---     0.101      R8C15C.C0 to      R8C15C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_160
ROUTE         1     0.000      R8C15C.F0 to R8C15C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_5 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i24  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i24  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13D.CLK to      R9C13D.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 (from Clock_c)
ROUTE         6     0.136      R9C13D.Q1 to R9C13D.D1      FrequencyMeter_inst/DoubleDabble_inst/BCD_24
CTOF_DEL    ---     0.101      R9C13D.D1 to      R9C13D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152
ROUTE         1     0.000      R9C13D.F1 to R9C13D.DI1     FrequencyMeter_inst/DoubleDabble_inst/n149 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i4  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13D.CLK to      R7C13D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 (from Clock_c)
ROUTE         3     0.136      R7C13D.Q0 to R7C13D.D1      FrequencyMeter_inst/DoubleDabble_inst/Counter_3
CTOF_DEL    ---     0.101      R7C13D.D1 to      R7C13D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173
ROUTE         1     0.000      R7C13D.F1 to R7C13D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Counter_4_N_326_4 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i22  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i23  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18C.CLK to      R7C18C.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 (from Clock_c)
ROUTE         1     0.136      R7C18C.Q1 to R7C18D.C0      FrequencyMeter_inst/DoubleDabble_inst/Binary_22
CTOF_DEL    ---     0.101      R7C18D.C0 to      R7C18D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_169
ROUTE         1     0.000      R7C18D.F0 to R7C18D.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_23 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i30  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i31  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C15A.CLK to      R9C15A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 (from Clock_c)
ROUTE         5     0.136      R9C15A.Q1 to R9C15C.D0      FrequencyMeter_inst/DoubleDabble_inst/BCD_30
CTOF_DEL    ---     0.101      R9C15C.D0 to      R9C15C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_156
ROUTE         1     0.000      R9C15C.F0 to R9C15C.DI0     FrequencyMeter_inst/DoubleDabble_inst/n142 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_156:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i13  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C16A.CLK to      R8C16A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 (from Clock_c)
ROUTE         1     0.136      R8C16A.Q1 to R8C16C.C0      FrequencyMeter_inst/DoubleDabble_inst/Binary_12
CTOF_DEL    ---     0.101      R8C16C.C0 to      R8C16C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_164
ROUTE         1     0.000      R8C16C.F0 to R8C16C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_13 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.383ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Binary_i11  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i12  (to Clock_c +)

   Delay:               0.370ns  (63.2% logic, 36.8% route), 2 logic levels.

 Constraint Details:

      0.370ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.383ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C16A.CLK to      R8C16A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_163 (from Clock_c)
ROUTE         1     0.136      R8C16A.Q0 to R8C16A.C1      FrequencyMeter_inst/DoubleDabble_inst/Binary_11
CTOF_DEL    ---     0.101      R8C16A.C1 to      R8C16A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_163
ROUTE         1     0.000      R8C16A.F1 to R8C16A.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_12 (to Clock_c)
                  --------
                    0.370   (63.2% logic, 36.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_163:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i13  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i13  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16D.CLK to      R7C16D.Q0 FrequencyMeter_inst/SLICE_73 (from Clock_c)
ROUTE         2     0.137      R7C16D.Q0 to R8C16C.D0      FrequencyMeter_inst/Counter_13
CTOF_DEL    ---     0.101      R8C16C.D0 to      R8C16C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_164
ROUTE         1     0.000      R8C16C.F0 to R8C16C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_13 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i5  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15D.CLK to      R7C15D.Q0 FrequencyMeter_inst/SLICE_77 (from Clock_c)
ROUTE         2     0.137      R7C15D.Q0 to R8C15C.D0      FrequencyMeter_inst/Counter_5
CTOF_DEL    ---     0.101      R8C15C.D0 to      R8C15C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_160
ROUTE         1     0.000      R8C15C.F0 to R8C15C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_5 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i1  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i1  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15B.CLK to      R7C15B.Q0 FrequencyMeter_inst/SLICE_79 (from Clock_c)
ROUTE         2     0.137      R7C15B.Q0 to R8C15A.D0      FrequencyMeter_inst/Counter_1
CTOF_DEL    ---     0.101      R8C15A.D0 to      R8C15A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_158
ROUTE         1     0.000      R8C15A.F0 to R8C15A.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_1 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/State_FSM_i0  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i1  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay EncoderAmpl_inst/SLICE_121 to EncoderAmpl_inst/SLICE_121 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_121 to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14A.CLK to      R5C14A.Q1 EncoderAmpl_inst/SLICE_121 (from Clock_c)
ROUTE         4     0.137      R5C14A.Q1 to R5C14A.D0      EncoderAmpl_inst/n252
CTOF_DEL    ---     0.101      R5C14A.D0 to      R5C14A.F0 EncoderAmpl_inst/SLICE_121
ROUTE         1     0.000      R5C14A.F0 to R5C14A.DI0     EncoderAmpl_inst/n1980 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i8  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16A.CLK to      R7C16A.Q1 FrequencyMeter_inst/SLICE_76 (from Clock_c)
ROUTE         2     0.137      R7C16A.Q1 to R8C16D.D1      FrequencyMeter_inst/Counter_8
CTOF_DEL    ---     0.101      R8C16D.D1 to      R8C16D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_161
ROUTE         1     0.000      R8C16D.F1 to R8C16D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_8 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i4  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i4  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15C.CLK to      R7C15C.Q1 FrequencyMeter_inst/SLICE_78 (from Clock_c)
ROUTE         2     0.137      R7C15C.Q1 to R8C15B.D1      FrequencyMeter_inst/Counter_4
CTOF_DEL    ---     0.101      R8C15B.D1 to      R8C15B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_159
ROUTE         1     0.000      R8C15B.F1 to R8C15B.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_4 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i16  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i16  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17A.CLK to      R7C17A.Q1 FrequencyMeter_inst/SLICE_72 (from Clock_c)
ROUTE         2     0.137      R7C17A.Q1 to R8C17D.D1      FrequencyMeter_inst/Counter_16
CTOF_DEL    ---     0.101      R8C17D.D1 to      R8C17D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_165
ROUTE         1     0.000      R8C17D.F1 to R8C17D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_16 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i3  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i3  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_78 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15C.CLK to      R7C15C.Q0 FrequencyMeter_inst/SLICE_78 (from Clock_c)
ROUTE         2     0.137      R7C15C.Q0 to R8C15B.D0      FrequencyMeter_inst/Counter_3
CTOF_DEL    ---     0.101      R8C15B.D0 to      R8C15B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_159
ROUTE         1     0.000      R8C15B.F0 to R8C15B.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_3 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_78:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_159:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i7  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_76 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16A.CLK to      R7C16A.Q0 FrequencyMeter_inst/SLICE_76 (from Clock_c)
ROUTE         2     0.137      R7C16A.Q0 to R8C16D.D0      FrequencyMeter_inst/Counter_7
CTOF_DEL    ---     0.101      R8C16D.D0 to      R8C16D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_161
ROUTE         1     0.000      R8C16D.F0 to R8C16D.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_7 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_76:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_161:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i15  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i15  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_72 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17A.CLK to      R7C17A.Q0 FrequencyMeter_inst/SLICE_72 (from Clock_c)
ROUTE         2     0.137      R7C17A.Q0 to R8C17D.D0      FrequencyMeter_inst/Counter_15
CTOF_DEL    ---     0.101      R8C17D.D0 to      R8C17D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_165
ROUTE         1     0.000      R8C17D.F0 to R8C17D.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_15 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_72:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_165:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i2  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_79 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15B.CLK to      R7C15B.Q1 FrequencyMeter_inst/SLICE_79 (from Clock_c)
ROUTE         2     0.137      R7C15B.Q1 to R8C15A.D1      FrequencyMeter_inst/Counter_2
CTOF_DEL    ---     0.101      R8C15A.D1 to      R8C15A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_158
ROUTE         1     0.000      R8C15A.F1 to R8C15A.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_2 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_79:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_158:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i6  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i6  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_77 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C15D.CLK to      R7C15D.Q1 FrequencyMeter_inst/SLICE_77 (from Clock_c)
ROUTE         2     0.137      R7C15D.Q1 to R8C15C.D1      FrequencyMeter_inst/Counter_6
CTOF_DEL    ---     0.101      R8C15C.D1 to      R8C15C.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_160
ROUTE         1     0.000      R8C15C.F1 to R8C15C.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_6 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_77:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_160:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C15C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.384ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i14  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i14  (to Clock_c +)

   Delay:               0.371ns  (63.1% logic, 36.9% route), 2 logic levels.

 Constraint Details:

      0.371ns physical path delay FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.384ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_73 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16D.CLK to      R7C16D.Q1 FrequencyMeter_inst/SLICE_73 (from Clock_c)
ROUTE         2     0.137      R7C16D.Q1 to R8C16C.D1      FrequencyMeter_inst/Counter_14
CTOF_DEL    ---     0.101      R8C16C.D1 to      R8C16C.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_164
ROUTE         1     0.000      R8C16C.F1 to R8C16C.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_14 (to Clock_c)
                  --------
                    0.371   (63.1% logic, 36.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_73:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_164:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.385ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i22  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i23  (to Clock_c +)

   Delay:               0.372ns  (62.9% logic, 37.1% route), 2 logic levels.

 Constraint Details:

      0.372ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.385ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13B.CLK to      R9C13B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_151 (from Clock_c)
ROUTE         5     0.138      R9C13B.Q1 to R9C13D.D0      FrequencyMeter_inst/DoubleDabble_inst/BCD_22
CTOF_DEL    ---     0.101      R9C13D.D0 to      R9C13D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152
ROUTE         1     0.000      R9C13D.F0 to R9C13D.DI0     FrequencyMeter_inst/DoubleDabble_inst/n150 (to Clock_c)
                  --------
                    0.372   (62.9% logic, 37.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_151:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.385ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i24  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i24  (to Clock_c +)

   Delay:               0.372ns  (62.9% logic, 37.1% route), 2 logic levels.

 Constraint Details:

      0.372ns physical path delay FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.385ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_68 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C18A.CLK to      R7C18A.Q1 FrequencyMeter_inst/SLICE_68 (from Clock_c)
ROUTE         2     0.138      R7C18A.Q1 to R7C18D.C1      FrequencyMeter_inst/Counter_24
CTOF_DEL    ---     0.101      R7C18D.C1 to      R7C18D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_169
ROUTE         1     0.000      R7C18D.F1 to R7C18D.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_24 (to Clock_c)
                  --------
                    0.372   (62.9% logic, 37.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_68:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_169:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.385ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              TuningWord_i0  (from Clock_c +)
   Destination:    FF         Data in        TuningWord_i0  (to Clock_c +)

   Delay:               0.372ns  (62.9% logic, 37.1% route), 2 logic levels.

 Constraint Details:

      0.372ns physical path delay SLICE_62 to SLICE_62 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.385ns

 Physical Path Details:

      Data path SLICE_62 to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133      R9C8B.CLK to       R9C8B.Q0 SLICE_62 (from Clock_c)
ROUTE         3     0.138       R9C8B.Q0 to R9C8B.C0       TuningWord_0
CTOF_DEL    ---     0.101       R9C8B.C0 to       R9C8B.F0 SLICE_62
ROUTE         1     0.000       R9C8B.F0 to R9C8B.DI0      TuningWord_7_N_1_0 (to Clock_c)
                  --------
                    0.372   (62.9% logic, 37.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_62:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C8B.CLK      Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/SynchronizerA/R2_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i0  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_121 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13D.CLK to      R5C13D.Q0 EncoderAmpl_inst/SLICE_206 (from Clock_c)
ROUTE         8     0.139      R5C13D.Q0 to R5C14A.D1      EncoderAmpl_inst/B
CTOF_DEL    ---     0.101      R5C14A.D1 to      R5C14A.F1 EncoderAmpl_inst/SLICE_121
ROUTE         1     0.000      R5C14A.F1 to R5C14A.DI1     EncoderAmpl_inst/n1264 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i7  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i7  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C14A.CLK to      R7C14A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 (from Clock_c)
ROUTE         5     0.139      R7C14A.Q1 to R7C14A.C1      FrequencyMeter_inst/DoubleDabble_inst/BCD_7
CTOF_DEL    ---     0.101      R7C14A.C1 to      R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_143
ROUTE         1     0.000      R7C14A.F1 to R7C14A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n166 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i21  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i21  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_69 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C17D.CLK to      R7C17D.Q0 FrequencyMeter_inst/SLICE_69 (from Clock_c)
ROUTE         2     0.139      R7C17D.Q0 to R7C18C.C0      FrequencyMeter_inst/Counter_21
CTOF_DEL    ---     0.101      R7C18C.C0 to      R7C18C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_168
ROUTE         1     0.000      R7C18C.F0 to R7C18C.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_21 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_69:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C17D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_168:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C18C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i5  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i6  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C14B.CLK to      R8C14B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_142 (from Clock_c)
ROUTE         6     0.139      R8C14B.Q1 to R7C14A.D0      FrequencyMeter_inst/DoubleDabble_inst/BCD_5
CTOF_DEL    ---     0.101      R7C14A.D0 to      R7C14A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_143
ROUTE         1     0.000      R7C14A.F0 to R7C14A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n167 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_142:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_143:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Counter_i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Counter_i3  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C13B.CLK to      R7C13B.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_172 (from Clock_c)
ROUTE         4     0.139      R7C13B.Q1 to R7C13D.C0      FrequencyMeter_inst/DoubleDabble_inst/Counter_2
CTOF_DEL    ---     0.101      R7C13D.C0 to      R7C13D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_173
ROUTE         1     0.000      R7C13D.F0 to R7C13D.DI0     FrequencyMeter_inst/DoubleDabble_inst/Counter_4_N_326_3 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_172:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_173:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/State_FSM_i0  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i1  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay EncoderFreq_inst/SLICE_126 to EncoderFreq_inst/SLICE_126 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_126 to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C15D.CLK to      R5C15D.Q1 EncoderFreq_inst/SLICE_126 (from Clock_c)
ROUTE         4     0.139      R5C15D.Q1 to R5C15D.C0      EncoderFreq_inst/n194
CTOF_DEL    ---     0.101      R5C15D.C0 to      R5C15D.F0 EncoderFreq_inst/SLICE_126
ROUTE         1     0.000      R5C15D.F0 to R5C15D.DI0     EncoderFreq_inst/n1976 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i23  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i23  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C13D.CLK to      R9C13D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152 (from Clock_c)
ROUTE         5     0.139      R9C13D.Q0 to R9C13D.C0      FrequencyMeter_inst/DoubleDabble_inst/BCD_23
CTOF_DEL    ---     0.101      R9C13D.C0 to      R9C13D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_152
ROUTE         1     0.000      R9C13D.F0 to R9C13D.DI0     FrequencyMeter_inst/DoubleDabble_inst/n150 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_152:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.386ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Amplitude_i0  (from Clock_c +)
   Destination:    FF         Data in        Amplitude_i0  (to Clock_c +)

   Delay:               0.373ns  (62.7% logic, 37.3% route), 2 logic levels.

 Constraint Details:

      0.373ns physical path delay SLICE_58 to SLICE_58 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.386ns

 Physical Path Details:

      Data path SLICE_58 to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C11B.CLK to      R5C11B.Q0 SLICE_58 (from Clock_c)
ROUTE         9     0.139      R5C11B.Q0 to R5C11B.C0      Amplitude_0
CTOF_DEL    ---     0.101      R5C11B.C0 to      R5C11B.F0 SLICE_58
ROUTE         1     0.000      R5C11B.F0 to R5C11B.DI0     Amplitude_7_N_11_0 (to Clock_c)
                  --------
                    0.373   (62.7% logic, 37.3% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to SLICE_58:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C11B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.387ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i18  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i19  (to Clock_c +)

   Delay:               0.374ns  (62.6% logic, 37.4% route), 2 logic levels.

 Constraint Details:

      0.374ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.387ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13A.CLK to      R8C13A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 (from Clock_c)
ROUTE         5     0.140      R8C13A.Q0 to R8C13A.C1      FrequencyMeter_inst/DoubleDabble_inst/BCD_18
CTOF_DEL    ---     0.101      R8C13A.C1 to      R8C13A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149
ROUTE         1     0.000      R8C13A.F1 to R8C13A.DI1     FrequencyMeter_inst/DoubleDabble_inst/n154 (to Clock_c)
                  --------
                    0.374   (62.6% logic, 37.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.387ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i9  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i9  (to Clock_c +)

   Delay:               0.374ns  (62.6% logic, 37.4% route), 2 logic levels.

 Constraint Details:

      0.374ns physical path delay FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.387ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16B.CLK to      R7C16B.Q0 FrequencyMeter_inst/SLICE_75 (from Clock_c)
ROUTE         2     0.140      R7C16B.Q0 to R8C16B.C0      FrequencyMeter_inst/Counter_9
CTOF_DEL    ---     0.101      R8C16B.C0 to      R8C16B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_162
ROUTE         1     0.000      R8C16B.F0 to R8C16B.DI0     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_9 (to Clock_c)
                  --------
                    0.374   (62.6% logic, 37.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.387ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Counter__i10  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/Binary_i10  (to Clock_c +)

   Delay:               0.374ns  (62.6% logic, 37.4% route), 2 logic levels.

 Constraint Details:

      0.374ns physical path delay FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.387ns

 Physical Path Details:

      Data path FrequencyMeter_inst/SLICE_75 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C16B.CLK to      R7C16B.Q1 FrequencyMeter_inst/SLICE_75 (from Clock_c)
ROUTE         2     0.140      R7C16B.Q1 to R8C16B.C1      FrequencyMeter_inst/Counter_10
CTOF_DEL    ---     0.101      R8C16B.C1 to      R8C16B.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_162
ROUTE         1     0.000      R8C16B.F1 to R8C16B.DI1     FrequencyMeter_inst/DoubleDabble_inst/Binary_25_N_268_10 (to Clock_c)
                  --------
                    0.374   (62.6% logic, 37.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/SLICE_75:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_162:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C16B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.387ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i2  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i3  (to Clock_c +)

   Delay:               0.374ns  (62.6% logic, 37.4% route), 2 logic levels.

 Constraint Details:

      0.374ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.387ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11D.CLK to      R7C11D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141 (from Clock_c)
ROUTE         5     0.140      R7C11D.Q0 to R7C11D.C1      FrequencyMeter_inst/DoubleDabble_inst/BCD_2
CTOF_DEL    ---     0.101      R7C11D.C1 to      R7C11D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_141
ROUTE         1     0.000      R7C11D.F1 to R7C11D.DI1     FrequencyMeter_inst/DoubleDabble_inst/n170 (to Clock_c)
                  --------
                    0.374   (62.6% logic, 37.4% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_141:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.388ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/State_FSM_i0  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i2  (to Clock_c +)

   Delay:               0.375ns  (62.4% logic, 37.6% route), 2 logic levels.

 Constraint Details:

      0.375ns physical path delay EncoderFreq_inst/SLICE_126 to EncoderFreq_inst/SLICE_125 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.388ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_126 to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C15D.CLK to      R5C15D.Q1 EncoderFreq_inst/SLICE_126 (from Clock_c)
ROUTE         4     0.141      R5C15D.Q1 to R5C15B.D1      EncoderFreq_inst/n194
CTOF_DEL    ---     0.101      R5C15B.D1 to      R5C15B.F1 EncoderFreq_inst/SLICE_125
ROUTE         1     0.000      R5C15B.F1 to R5C15B.DI1     EncoderFreq_inst/n1974 (to Clock_c)
                  --------
                    0.375   (62.4% logic, 37.6% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.389ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i19  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i20  (to Clock_c +)

   Delay:               0.376ns  (62.2% logic, 37.8% route), 2 logic levels.

 Constraint Details:

      0.376ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.389ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R8C13A.CLK to      R8C13A.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_149 (from Clock_c)
ROUTE         5     0.142      R8C13A.Q1 to R9C13A.C0      FrequencyMeter_inst/DoubleDabble_inst/BCD_19
CTOF_DEL    ---     0.101      R9C13A.C0 to      R9C13A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_150
ROUTE         1     0.000      R9C13A.F0 to R9C13A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n153 (to Clock_c)
                  --------
                    0.376   (62.2% logic, 37.8% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_149:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_150:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C13A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.389ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/Synchronizer_inst/R1_0__8  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/Synchronizer_inst/R2_0__9  (to Clock_c +)

   Delay:               0.370ns  (35.9% logic, 64.1% route), 1 logic levels.

 Constraint Details:

      0.370ns physical path delay SLICE_176 to FrequencyMeter_inst/SLICE_181 meets
     -0.019ns M_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.019ns) by 0.389ns

 Physical Path Details:

      Data path SLICE_176 to FrequencyMeter_inst/SLICE_181:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C11A.CLK to      R7C11A.Q0 SLICE_176 (from Clock_c)
ROUTE         1     0.237      R7C11A.Q0 to R8C13D.M0      FrequencyMeter_inst/Synchronizer_inst/R1_0 (to Clock_c)
                  --------
                    0.370   (35.9% logic, 64.1% route), 1 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to SLICE_176:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C11A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/SLICE_181:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R8C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.390ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/SynchronizerA/R2_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i1  (to Clock_c +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_121 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13D.CLK to      R5C13D.Q0 EncoderAmpl_inst/SLICE_206 (from Clock_c)
ROUTE         8     0.143      R5C13D.Q0 to R5C14A.C0      EncoderAmpl_inst/B
CTOF_DEL    ---     0.101      R5C14A.C0 to      R5C14A.F0 EncoderAmpl_inst/SLICE_121
ROUTE         1     0.000      R5C14A.F0 to R5C14A.DI0     EncoderAmpl_inst/n1980 (to Clock_c)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_121:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.390ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/State_FSM_i2  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i2  (to Clock_c +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay EncoderFreq_inst/SLICE_125 to EncoderFreq_inst/SLICE_125 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_125 to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C15B.CLK to      R5C15B.Q1 EncoderFreq_inst/SLICE_125 (from Clock_c)
ROUTE         4     0.143      R5C15B.Q1 to R5C15B.C1      EncoderFreq_inst/n192
CTOF_DEL    ---     0.101      R5C15B.C1 to      R5C15B.F1 EncoderFreq_inst/SLICE_125
ROUTE         1     0.000      R5C15B.F1 to R5C15B.DI1     EncoderFreq_inst/n1974 (to Clock_c)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_125:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.390ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i28  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i29  (to Clock_c +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 (from Clock_c)
ROUTE         6     0.143      R9C14C.Q1 to R9C15A.C0      FrequencyMeter_inst/DoubleDabble_inst/BCD_28
CTOF_DEL    ---     0.101      R9C15A.C0 to      R9C15A.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_155
ROUTE         1     0.000      R9C15A.F0 to R9C15A.DI0     FrequencyMeter_inst/DoubleDabble_inst/n144 (to Clock_c)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_155:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C15A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.390ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/SynchronizerA/R2_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i1  (to Clock_c +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay EncoderFreq_inst/SLICE_220 to EncoderFreq_inst/SLICE_126 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_220 to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14B.CLK to      R5C14B.Q0 EncoderFreq_inst/SLICE_220 (from Clock_c)
ROUTE         8     0.143      R5C14B.Q0 to R5C15D.D0      EncoderFreq_inst/B
CTOF_DEL    ---     0.101      R5C15D.D0 to      R5C15D.F0 EncoderFreq_inst/SLICE_126
ROUTE         1     0.000      R5C15D.F0 to R5C15D.DI0     EncoderFreq_inst/n1976 (to Clock_c)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.390ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderFreq_inst/SynchronizerA/R2_i1  (from Clock_c +)
   Destination:    FF         Data in        EncoderFreq_inst/State_FSM_i0  (to Clock_c +)

   Delay:               0.377ns  (62.1% logic, 37.9% route), 2 logic levels.

 Constraint Details:

      0.377ns physical path delay EncoderFreq_inst/SLICE_220 to EncoderFreq_inst/SLICE_126 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.390ns

 Physical Path Details:

      Data path EncoderFreq_inst/SLICE_220 to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C14B.CLK to      R5C14B.Q0 EncoderFreq_inst/SLICE_220 (from Clock_c)
ROUTE         8     0.143      R5C14B.Q0 to R5C15D.D1      EncoderFreq_inst/B
CTOF_DEL    ---     0.101      R5C15D.D1 to      R5C15D.F1 EncoderFreq_inst/SLICE_126
ROUTE         1     0.000      R5C15D.F1 to R5C15D.DI1     EncoderFreq_inst/n1267 (to Clock_c)
                  --------
                    0.377   (62.1% logic, 37.9% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderFreq_inst/SLICE_220:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderFreq_inst/SLICE_126:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C15D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i12  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C10D.CLK to      R9C10D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 (from Clock_c)
ROUTE         6     0.144      R9C10D.Q0 to R9C10D.D0      FrequencyMeter_inst/DoubleDabble_inst/BCD_12
CTOF_DEL    ---     0.101      R9C10D.D0 to      R9C10D.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_146
ROUTE         1     0.000      R9C10D.F0 to R9C10D.DI0     FrequencyMeter_inst/DoubleDabble_inst/n161 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              EncoderAmpl_inst/SynchronizerA/R2_i2  (from Clock_c +)
   Destination:    FF         Data in        EncoderAmpl_inst/State_FSM_i2  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_120 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path EncoderAmpl_inst/SLICE_206 to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R5C13D.CLK to      R5C13D.Q1 EncoderAmpl_inst/SLICE_206 (from Clock_c)
ROUTE         8     0.144      R5C13D.Q1 to R5C13C.C1      EncoderAmpl_inst/A
CTOF_DEL    ---     0.101      R5C13C.C1 to      R5C13C.F1 EncoderAmpl_inst/SLICE_120
ROUTE         1     0.000      R5C13C.F1 to R5C13C.DI1     EncoderAmpl_inst/n1978 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to EncoderAmpl_inst/SLICE_206:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to EncoderAmpl_inst/SLICE_120:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R5C13C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i27  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i27  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 (from Clock_c)
ROUTE         5     0.144      R9C14C.Q0 to R9C14C.D0      FrequencyMeter_inst/DoubleDabble_inst/BCD_27
CTOF_DEL    ---     0.101      R9C14C.D0 to      R9C14C.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154
ROUTE         1     0.000      R9C14C.F0 to R9C14C.DI0     FrequencyMeter_inst/DoubleDabble_inst/n146 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i12  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i13  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C10D.CLK to      R9C10D.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_146 (from Clock_c)
ROUTE         6     0.144      R9C10D.Q0 to R9C10D.D1      FrequencyMeter_inst/DoubleDabble_inst/BCD_12
CTOF_DEL    ---     0.101      R9C10D.D1 to      R9C10D.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_146
ROUTE         1     0.000      R9C10D.F1 to R9C10D.DI1     FrequencyMeter_inst/DoubleDabble_inst/n160 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_146:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C10D.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/BCD__i27  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/BCD__i28  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R9C14C.CLK to      R9C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154 (from Clock_c)
ROUTE         5     0.144      R9C14C.Q0 to R9C14C.D1      FrequencyMeter_inst/DoubleDabble_inst/BCD_27
CTOF_DEL    ---     0.101      R9C14C.D1 to      R9C14C.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_154
ROUTE         1     0.000      R9C14C.F1 to R9C14C.DI1     FrequencyMeter_inst/DoubleDabble_inst/n145 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_154:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R9C14C.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.
 

Passed: The following path meets requirements by 0.391ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FrequencyMeter_inst/DoubleDabble_inst/Busy_o_90  (from Clock_c +)
   Destination:    FF         Data in        FrequencyMeter_inst/DoubleDabble_inst/State_95  (to Clock_c +)

   Delay:               0.378ns  (61.9% logic, 38.1% route), 2 logic levels.

 Constraint Details:

      0.378ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint less
      0.000ns skew requirement (totaling -0.013ns) by 0.391ns

 Physical Path Details:

      Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133     R7C12A.CLK to      R7C12A.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 (from Clock_c)
ROUTE         8     0.144      R7C12A.Q0 to R7C14B.C0      Busy_o
CTOF_DEL    ---     0.101      R7C14B.C0 to      R7C14B.F0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_174
ROUTE         1     0.000      R7C14B.F0 to R7C14B.DI0     FrequencyMeter_inst/DoubleDabble_inst/State_N_434 (to Clock_c)
                  --------
                    0.378   (61.9% logic, 38.1% route), 2 logic levels.

 Clock Skew Details: 

      Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_103:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C12A.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

      Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_174:

   Name    Fanout   Delay (ns)          Site               Resource
ROUTE       135     0.773       20.PADDI to R7C14B.CLK     Clock_c
                  --------
                    0.773   (0.0% logic, 100.0% route), 0 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "Clock_c" 25.000000 MHz ; |     0.000 ns|     0.238 ns|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: Clock_c   Source: Clock.PAD   Loads: 135
   Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ;


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 30733 paths, 1 nets, and 1430 connections (86.35% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)