Place & Route TRACE Report

Loading design for application trce from file kurs25_impl1.ncd.
Design name: top
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Sat Mar 30 12:07:00 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs25_impl1.twr -gui -msgset C:/Lattice/Kurs25/promote.xml Kurs25_impl1.ncd Kurs25_impl1.prf 
Design file:     kurs25_impl1.ncd
Preference file: kurs25_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 3665 items scored, 0 timing errors detected. Report: 133.923MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 3665 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 32.533ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i1 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i0 Delay: 7.218ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.218ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_250 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.533ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_250: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.717 R7C14A.F1 to R7C12D.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.218 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_250: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R7C12D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.533ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i9 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i8 Delay: 7.218ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.218ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to SLICE_256 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.533ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to SLICE_256: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.717 R7C14A.F1 to R7C12C.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.218 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_256: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R7C12C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i3 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i29 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/SLICE_264 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/SLICE_264: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R8C15D.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/SLICE_264: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R8C15D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i11 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i10 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R5C14B.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R5C14B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i26 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i25 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R5C15C.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R5C15C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i19 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i18 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_243 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_243: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R4C13B.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_243: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C13B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i28 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i27 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/SLICE_263 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/SLICE_263: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R7C13D.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/SLICE_263: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R7C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i13 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i12 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_222: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R4C14A.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_222: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i22 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i21 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R5C14D.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R5C14D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.547ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/Counter_i1 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i24 (to Clock_c +) FF FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i23 Delay: 7.204ns (24.5% logic, 75.5% route), 4 logic levels. Constraint Details: 7.204ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_247 meets 40.000ns delay constraint less 0.000ns skew and 0.249ns CE_SET requirement (totaling 39.751ns) by 32.547ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_247: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R4C14C.CLK to R4C14C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_202 (from Clock_c) ROUTE 5 0.870 R4C14C.Q0 to R4C15D.A1 FrequencyMeter_inst/DoubleDabble_inst/Counter_1 CTOF_DEL --- 0.452 R4C15D.A1 to R4C15D.F1 SLICE_213 ROUTE 1 0.656 R4C15D.F1 to R4C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n6 CTOF_DEL --- 0.452 R4C14A.C1 to R4C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_222 ROUTE 7 1.210 R4C14A.F1 to R7C14A.C1 FrequencyMeter_inst/DoubleDabble_inst/n2143 CTOF_DEL --- 0.452 R7C14A.C1 to R7C14A.F1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_103 ROUTE 16 2.703 R7C14A.F1 to R7C15C.CE FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (to Clock_c) -------- 7.204 (24.5% logic, 75.5% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_202: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R4C14C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_247: Name Fanout Delay (ns) Site Resource ROUTE 192 2.001 20.PADDI to R7C15C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Report: 133.923MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 25.000 MHz| 133.923 MHz| 4 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 192 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 3665 paths, 1 nets, and 1602 connections (87.64% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2 Sat Mar 30 12:07:00 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs25_impl1.twr -gui -msgset C:/Lattice/Kurs25/promote.xml Kurs25_impl1.ncd Kurs25_impl1.prf Design file: kurs25_impl1.ncd Preference file: kurs25_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 3665 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 3665 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q EncoderFreq_inst/SynchronizerA/R1_i1 (from Clock_c +) Destination: FF Data in EncoderFreq_inst/SynchronizerA/R2_i1 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_236 to SLICE_265 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_236 to SLICE_265: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12C.CLK to R9C12C.Q1 SLICE_236 (from Clock_c) ROUTE 1 0.152 R9C12C.Q1 to R9C12B.M1 EncoderFreq_inst/SynchronizerA/R1_1 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_236: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_265: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q EncoderAmpl_inst/SynchronizerA/R1_i2 (from Clock_c +) Destination: FF Data in EncoderAmpl_inst/SynchronizerA/R2_i2 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_239 to SLICE_236 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_239 to SLICE_236: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12A.CLK to R9C12A.Q0 SLICE_239 (from Clock_c) ROUTE 1 0.152 R9C12A.Q0 to R9C12C.M0 EncoderAmpl_inst/SynchronizerA/R1_2 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_239: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_236: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.304ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q EncoderFreq_inst/SynchronizerA/R1_i2 (from Clock_c +) Destination: FF Data in EncoderFreq_inst/SynchronizerA/R2_i2 (to Clock_c +) Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels. Constraint Details: 0.285ns physical path delay SLICE_265 to SLICE_235 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.304ns Physical Path Details: Data path SLICE_265 to SLICE_235: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C12B.CLK to R9C12B.Q0 SLICE_265 (from Clock_c) ROUTE 1 0.152 R9C12B.Q0 to R9C12D.M0 EncoderFreq_inst/SynchronizerA/R1_2 (to Clock_c) -------- 0.285 (46.7% logic, 53.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_265: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_235: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R9C12D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DDS_inst/multiplier_inst/FF_44 (from Clock_c +) Destination: FF Data in DDS_inst/multiplier_inst/FF_10 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay DDS_inst/multiplier_inst/SLICE_50 to DDS_inst/multiplier_inst/SLICE_17 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path DDS_inst/multiplier_inst/SLICE_50 to DDS_inst/multiplier_inst/SLICE_17: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R10C8B.CLK to R10C8B.Q0 DDS_inst/multiplier_inst/SLICE_50 (from Clock_c) ROUTE 1 0.154 R10C8B.Q0 to R10C7B.M1 DDS_inst/multiplier_inst/f_Multiplier_0_pp_2_5 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/multiplier_inst/SLICE_50: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R10C8B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/multiplier_inst/SLICE_17: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R10C7B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/Synchronizer_inst/R1_0__8 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/Synchronizer_inst/R2_0__9 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_206 to SLICE_211 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_206 to SLICE_211: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C12B.CLK to R7C12B.Q0 SLICE_206 (from Clock_c) ROUTE 1 0.154 R7C12B.Q0 to R7C11B.M0 FrequencyMeter_inst/Synchronizer_inst/R1_0 (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_206: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R7C12B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_211: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R7C11B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/Synchronizer_inst/R2_0__9 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/EdgeDetector_inst/Previous_13 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_211 to SLICE_211 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_211 to SLICE_211: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C11B.CLK to R7C11B.Q0 SLICE_211 (from Clock_c) ROUTE 2 0.154 R7C11B.Q0 to R7C11B.M1 SignalSync (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_211: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R7C11B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_211: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R7C11B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.307ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/BCD__i26 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i26 (to Clock_c +) Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels. Constraint Details: 0.288ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_183 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.307ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_183 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C15D.CLK to R5C15D.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_183 (from Clock_c) ROUTE 5 0.155 R5C15D.Q1 to R5C15C.M1 FrequencyMeter_inst/DoubleDabble_inst/BCD_26 (to Clock_c) -------- 0.288 (46.2% logic, 53.8% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_183: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C15D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_249: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C15C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.310ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/BCD__i16 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i16 (to Clock_c +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_178 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_248 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.310ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_178 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_248: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R4C13C.CLK to R4C13C.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_178 (from Clock_c) ROUTE 6 0.158 R4C13C.Q0 to R4C12C.M0 FrequencyMeter_inst/DoubleDabble_inst/BCD_16 (to Clock_c) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_178: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R4C13C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_248: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R4C12C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.313ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/BCD__i10 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i10 (to Clock_c +) Delay: 0.294ns (45.2% logic, 54.8% route), 1 logic levels. Constraint Details: 0.294ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_175 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.313ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_175 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C13B.CLK to R5C13B.Q0 FrequencyMeter_inst/DoubleDabble_inst/SLICE_175 (from Clock_c) ROUTE 5 0.161 R5C13B.Q0 to R5C14B.M0 FrequencyMeter_inst/DoubleDabble_inst/BCD_10 (to Clock_c) -------- 0.294 (45.2% logic, 54.8% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_175: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C13B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_257: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C14B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.313ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q FrequencyMeter_inst/DoubleDabble_inst/BCD__i22 (from Clock_c +) Destination: FF Data in FrequencyMeter_inst/DoubleDabble_inst/BCD_o_i0_i22 (to Clock_c +) Delay: 0.294ns (45.2% logic, 54.8% route), 1 logic levels. Constraint Details: 0.294ns physical path delay FrequencyMeter_inst/DoubleDabble_inst/SLICE_181 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.313ns Physical Path Details: Data path FrequencyMeter_inst/DoubleDabble_inst/SLICE_181 to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R5C14C.CLK to R5C14C.Q1 FrequencyMeter_inst/DoubleDabble_inst/SLICE_181 (from Clock_c) ROUTE 5 0.161 R5C14C.Q1 to R5C14D.M1 FrequencyMeter_inst/DoubleDabble_inst/BCD_22 (to Clock_c) -------- 0.294 (45.2% logic, 54.8% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_181: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C14C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to FrequencyMeter_inst/DoubleDabble_inst/SLICE_245: Name Fanout Delay (ns) Site Resource ROUTE 192 0.773 20.PADDI to R5C14D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 0.000 ns| 0.304 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 192 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 3665 paths, 1 nets, and 1602 connections (87.64% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------