PAR: Place And Route Diamond (64-bit) 3.13.0.56.2. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Sat Mar 30 12:06:53 2024 C:/lscc/diamond/3.13/ispfpga\bin\nt64\par -f Kurs25_impl1.p2t Kurs25_impl1_map.ncd Kurs25_impl1.dir Kurs25_impl1.prf -gui -msgset C:/Lattice/Kurs25/promote.xml Preference file: Kurs25_impl1.prf. Cost Table Summary Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ 5_1 * 0 32.533 0 0.304 0 06 Completed * : Design saved. Total (real) run time for 1-seed: 6 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "Kurs25_impl1_map.ncd" Sat Mar 30 12:06:53 2024 Best Par Run PAR: Place And Route Diamond (64-bit) 3.13.0.56.2. Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Lattice/Kurs25/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 Kurs25_impl1_map.ncd Kurs25_impl1.dir/5_1.ncd Kurs25_impl1.prf Preference file: Kurs25_impl1.prf. Placement level-cost: 5-1. Routing Iterations: 6 Loading design for application par from file Kurs25_impl1_map.ncd. Design name: top NCD version: 3.3 Vendor: LATTICE Device: LCMXO2-1200HC Package: TQFP100 Performance: 5 Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga. Package Status: Final Version 1.44. Performance Hardware Data Status: Final Version 34.4. License checked out. Ignore Preference Error(s): True Device utilization summary: PIO (prelim) 30+4(JTAG)/108 31% used 30+4(JTAG)/80 43% bonded SLICE 215/640 33% used GSR 1/1 100% used EBR 1/7 14% used INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific data sheet for additional details. INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state. Number of Signals: 833 Number of Connections: 1828 Pin Constraint Summary: 30 out of 30 pins locked (100% locked). The following 1 signal is selected to use the primary clock routing resources: Clock_c (driver: Clock, clk load #: 192) The following 6 signals are selected to use the secondary clock routing resources: FrequencyMeter_inst/n2255 (driver: SLICE_206, clk load #: 0, sr load #: 27, ce load #: 0) Clock_c_enable_94 (driver: SLICE_256, clk load #: 0, sr load #: 0, ce load #: 17) FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125 (driver: FrequencyMeter_inst/DoubleDabble_inst/SLICE_103, clk load #: 0, sr load #: 0, ce load #: 16) Clock_c_enable_63 (driver: SLICE_200, clk load #: 0, sr load #: 0, ce load #: 14) FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_37 (driver: FrequencyMeter_inst/DoubleDabble_inst/SLICE_250, clk load #: 0, sr load #: 0, ce load #: 14) FrequencyMeter_inst/StrobeGenerator_inst/Strobe_o_N_225 (driver: FrequencyMeter_inst/StrobeGenerator_inst/SLICE_205, clk load #: 0, sr load #: 13, ce load #: 0) Signal Reset_c is selected as Global Set/Reset. Starting Placer Phase 0. .......... Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. ................... Placer score = 68170. Finished Placer Phase 1. REAL time: 5 secs Starting Placer Phase 2. . Placer score = 67098 Finished Placer Phase 2. REAL time: 5 secs Clock Report Global Clock Resources: CLK_PIN : 1 out of 8 (12%) PLL : 0 out of 1 (0%) DCM : 0 out of 2 (0%) DCC : 0 out of 8 (0%) Global Clocks: PRIMARY "Clock_c" from comp "Clock" on CLK_PIN site "20 (PL9A)", clk load = 192 SECONDARY "FrequencyMeter_inst/n2255" from Q1 on comp "SLICE_206" on site "R7C12B", clk load = 0, ce load = 0, sr load = 27 SECONDARY "Clock_c_enable_94" from F0 on comp "SLICE_256" on site "R7C12C", clk load = 0, ce load = 17, sr load = 0 SECONDARY "FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125" from F1 on comp "FrequencyMeter_inst/DoubleDabble_inst/SLICE_103" on site "R7C14A", clk load = 0, ce load = 16, sr load = 0 SECONDARY "Clock_c_enable_63" from F1 on comp "SLICE_200" on site "R7C12A", clk load = 0, ce load = 14, sr load = 0 SECONDARY "FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_37" from F0 on comp "FrequencyMeter_inst/DoubleDabble_inst/SLICE_250" on site "R7C12D", clk load = 0, ce load = 14, sr load = 0 SECONDARY "FrequencyMeter_inst/StrobeGenerator_inst/Strobe_o_N_225" from F0 on comp "FrequencyMeter_inst/StrobeGenerator_inst/SLICE_205" on site "R7C14D", clk load = 0, ce load = 0, sr load = 13 PRIMARY : 1 out of 8 (12%) SECONDARY: 6 out of 8 (75%) Edge Clocks: No edge clock selected. I/O Usage Summary (final): 30 + 4(JTAG) out of 108 (31.5%) PIO sites used. 30 + 4(JTAG) out of 80 (42.5%) bonded PIO sites used. Number of PIO comps: 30; differential: 0. Number of Vref pins used: 0. I/O Bank Usage Summary: +----------+----------------+------------+-----------+ | I/O Bank | Usage | Bank Vccio | Bank Vref | +----------+----------------+------------+-----------+ | 0 | 4 / 19 ( 21%) | 3.3V | - | | 1 | 5 / 21 ( 23%) | 3.3V | - | | 2 | 14 / 20 ( 70%) | 3.3V | - | | 3 | 7 / 20 ( 35%) | 3.3V | - | +----------+----------------+------------+-----------+ Total placer CPU time: 4 secs Dumping design to file Kurs25_impl1.dir/5_1.ncd. 0 connections routed; 1828 unrouted. Starting router resource preassignment Completed router resource preassignment. Real time: 5 secs Start NBR router at 12:06:58 03/30/24 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) in the earlier iterations. In each iteration, it tries to solve the conflicts while keeping the critical connections routed as short as possible. The routing process is said to be completed when no conflicts exist and all connections are routed. Note: NBR uses a different method to calculate timing slacks. The worst slack and total negative slack may not be the same as that in TRCE report. You should always run TRCE to verify your design. ***************************************************************** Start NBR special constraint process at 12:06:59 03/30/24 Start NBR section for initial routing at 12:06:59 03/30/24 Level 4, iteration 1 34(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) Start NBR section for normal routing at 12:06:59 03/30/24 Level 4, iteration 1 21(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Level 4, iteration 2 7(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Level 4, iteration 3 2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Level 4, iteration 4 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Start NBR section for setup/hold timing optimization with effort level 3 at 12:06:59 03/30/24 Start NBR section for re-routing at 12:06:59 03/30/24 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; Estimated worst slack/total negative slack<setup>: 32.533ns/0.000ns; real time: 6 secs Start NBR section for post-routing at 12:06:59 03/30/24 End NBR router with 0 unrouted connection NBR Summary ----------- Number of unrouted connections : 0 (0.00%) Number of connections with timing violations : 0 (0.00%) Estimated worst slack<setup> : 32.533ns Timing score<setup> : 0 ----------- Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored. Total CPU time 5 secs Total REAL time: 6 secs Completely routed. End of route. 1828 routed (100.00%); 0 unrouted. Hold time timing score: 0, hold timing errors: 0 Timing score: 0 Dumping design to file Kurs25_impl1.dir/5_1.ncd. All signals are completely routed. PAR_SUMMARY::Run status = Completed PAR_SUMMARY::Number of unrouted conns = 0 PAR_SUMMARY::Worst slack<setup/<ns>> = 32.533 PAR_SUMMARY::Timing score<setup/<ns>> = 0.000 PAR_SUMMARY::Worst slack<hold /<ns>> = 0.304 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 Total CPU time to completion: 5 secs Total REAL time to completion: 6 secs par done! Note: user must run 'Trace' for timing closure signoff. Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.