-------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2 Wed Mar 27 21:13:03 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: top Device,speed: LCMXO2-1200HC,5 Report level: verbose report, limited to 200 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 200 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 23.905ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.792ns (60.5% logic, 39.5% route), 11 logic levels. Constraint Details: 15.792ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 23.905ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.792 (60.5% logic, 39.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 23.961ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.736ns (60.5% logic, 39.5% route), 10 logic levels. Constraint Details: 15.736ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 23.961ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.736 (60.5% logic, 39.5% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 23.972ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.725ns (60.3% logic, 39.7% route), 11 logic levels. Constraint Details: 15.725ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 23.972ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.725 (60.3% logic, 39.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 23.999ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.698ns (60.3% logic, 39.7% route), 10 logic levels. Constraint Details: 15.698ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 23.999ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.698 (60.3% logic, 39.7% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.028ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.669ns (60.4% logic, 39.6% route), 10 logic levels. Constraint Details: 15.669ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.028ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.669 (60.4% logic, 39.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.037ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.660ns (61.0% logic, 39.0% route), 11 logic levels. Constraint Details: 15.660ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.037ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.660 (61.0% logic, 39.0% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.051ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.646ns (60.1% logic, 39.9% route), 10 logic levels. Constraint Details: 15.646ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.051ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.646 (60.1% logic, 39.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.055ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.642ns (60.3% logic, 39.7% route), 9 logic levels. Constraint Details: 15.642ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.055ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.642 (60.3% logic, 39.7% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.066ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.631ns (60.1% logic, 39.9% route), 10 logic levels. Constraint Details: 15.631ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.066ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.631 (60.1% logic, 39.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.104ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.593ns (60.8% logic, 39.2% route), 11 logic levels. Constraint Details: 15.593ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.104ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.593 (60.8% logic, 39.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.104ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.593ns (60.8% logic, 39.2% route), 11 logic levels. Constraint Details: 15.593ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.104ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.593 (60.8% logic, 39.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.104ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.593ns (60.8% logic, 39.2% route), 11 logic levels. Constraint Details: 15.593ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.104ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.593 (60.8% logic, 39.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.107ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.590ns (60.2% logic, 39.8% route), 9 logic levels. Constraint Details: 15.590ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.107ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.590 (60.2% logic, 39.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.118ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.579ns (60.0% logic, 40.0% route), 10 logic levels. Constraint Details: 15.579ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.118ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.579 (60.0% logic, 40.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.122ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.575ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.575ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.122ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.575 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.131ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.566ns (60.8% logic, 39.2% route), 10 logic levels. Constraint Details: 15.566ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.131ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.566 (60.8% logic, 39.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.145ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.552ns (59.9% logic, 40.1% route), 9 logic levels. Constraint Details: 15.552ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.145ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.552 (59.9% logic, 40.1% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.160ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.537ns (60.9% logic, 39.1% route), 10 logic levels. Constraint Details: 15.537ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.160ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.537 (60.9% logic, 39.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.171ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.526ns (60.7% logic, 39.3% route), 11 logic levels. Constraint Details: 15.526ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.171ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.526 (60.7% logic, 39.3% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.171ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.526ns (60.7% logic, 39.3% route), 11 logic levels. Constraint Details: 15.526ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.171ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.526 (60.7% logic, 39.3% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.174ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.523ns (60.0% logic, 40.0% route), 9 logic levels. Constraint Details: 15.523ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.174ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.523 (60.0% logic, 40.0% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.183ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.514ns (60.6% logic, 39.4% route), 10 logic levels. Constraint Details: 15.514ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.183ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.514 (60.6% logic, 39.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.197ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.500ns (59.8% logic, 40.2% route), 9 logic levels. Constraint Details: 15.500ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.197ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.500 (59.8% logic, 40.2% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.499ns (60.6% logic, 39.4% route), 10 logic levels. Constraint Details: 15.499ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.198ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.499 (60.6% logic, 39.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.499ns (60.6% logic, 39.4% route), 10 logic levels. Constraint Details: 15.499ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.198ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.499 (60.6% logic, 39.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.499ns (60.6% logic, 39.4% route), 10 logic levels. Constraint Details: 15.499ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.198ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.499 (60.6% logic, 39.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.201ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.496ns (59.9% logic, 40.1% route), 8 logic levels. Constraint Details: 15.496ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.201ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.496 (59.9% logic, 40.1% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.212ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.485ns (59.7% logic, 40.3% route), 9 logic levels. Constraint Details: 15.485ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.212ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.485 (59.7% logic, 40.3% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.227ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.470ns (60.7% logic, 39.3% route), 10 logic levels. Constraint Details: 15.470ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.227ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.470 (60.7% logic, 39.3% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.234ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.463ns (61.8% logic, 38.2% route), 11 logic levels. Constraint Details: 15.463ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.234ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.463 (61.8% logic, 38.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.241ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.456ns (62.8% logic, 37.2% route), 12 logic levels. Constraint Details: 15.456ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.241ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.456 (62.8% logic, 37.2% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.250ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.447ns (60.5% logic, 39.5% route), 10 logic levels. Constraint Details: 15.447ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.250ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.447 (60.5% logic, 39.5% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.250ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.447ns (60.5% logic, 39.5% route), 10 logic levels. Constraint Details: 15.447ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.250ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.447 (60.5% logic, 39.5% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.250ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.447ns (60.5% logic, 39.5% route), 10 logic levels. Constraint Details: 15.447ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.250ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.447 (60.5% logic, 39.5% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.253ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.444ns (59.8% logic, 40.2% route), 8 logic levels. Constraint Details: 15.444ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.253ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.444 (59.8% logic, 40.2% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.254ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.443ns (60.7% logic, 39.3% route), 9 logic levels. Constraint Details: 15.443ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.254ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.443 (60.7% logic, 39.3% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.263ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.434ns (62.9% logic, 37.1% route), 12 logic levels. Constraint Details: 15.434ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.263ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.434 (62.9% logic, 37.1% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.264ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.433ns (59.6% logic, 40.4% route), 9 logic levels. Constraint Details: 15.433ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.264ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.433 (59.6% logic, 40.4% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.265ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.432ns (60.4% logic, 39.6% route), 10 logic levels. Constraint Details: 15.432ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.265ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.432 (60.4% logic, 39.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.265ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.432ns (60.4% logic, 39.6% route), 10 logic levels. Constraint Details: 15.432ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.265ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.432 (60.4% logic, 39.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.268ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.429ns (59.8% logic, 40.2% route), 8 logic levels. Constraint Details: 15.429ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.268ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.429 (59.8% logic, 40.2% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.277ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.420ns (60.4% logic, 39.6% route), 9 logic levels. Constraint Details: 15.420ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.277ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.420 (60.4% logic, 39.6% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.290ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.407ns (61.8% logic, 38.2% route), 10 logic levels. Constraint Details: 15.407ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.290ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.407 (61.8% logic, 38.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.391ns (60.5% logic, 39.5% route), 9 logic levels. Constraint Details: 15.391ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.306ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.391 (60.5% logic, 39.5% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.389ns (62.6% logic, 37.4% route), 12 logic levels. Constraint Details: 15.389ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.308ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.389 (62.6% logic, 37.4% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.389ns (62.6% logic, 37.4% route), 12 logic levels. Constraint Details: 15.389ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.308ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.389 (62.6% logic, 37.4% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.317ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.380ns (60.3% logic, 39.7% route), 10 logic levels. Constraint Details: 15.380ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.317ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.380 (60.3% logic, 39.7% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.317ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.380ns (60.3% logic, 39.7% route), 10 logic levels. Constraint Details: 15.380ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.317ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.380 (60.3% logic, 39.7% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.320ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.377ns (59.6% logic, 40.4% route), 8 logic levels. Constraint Details: 15.377ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.320ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.377 (59.6% logic, 40.4% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.321ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.376ns (60.5% logic, 39.5% route), 9 logic levels. Constraint Details: 15.376ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.321ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.376 (60.5% logic, 39.5% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.328ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.369ns (61.6% logic, 38.4% route), 10 logic levels. Constraint Details: 15.369ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.328ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.369 (61.6% logic, 38.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.329ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.368ns (60.3% logic, 39.7% route), 9 logic levels. Constraint Details: 15.368ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.329ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.368 (60.3% logic, 39.7% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.330ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.367ns (62.7% logic, 37.3% route), 12 logic levels. Constraint Details: 15.367ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.330ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.367 (62.7% logic, 37.3% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.331ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.366ns (63.0% logic, 37.0% route), 11 logic levels. Constraint Details: 15.366ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.331ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.366 (63.0% logic, 37.0% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.335ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.362ns (62.5% logic, 37.5% route), 11 logic levels. Constraint Details: 15.362ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.335ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.362 (62.5% logic, 37.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.344ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.353ns (60.2% logic, 39.8% route), 9 logic levels. Constraint Details: 15.353ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.344ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.353 (60.2% logic, 39.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.344ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.353ns (60.2% logic, 39.8% route), 9 logic levels. Constraint Details: 15.353ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.344ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.353 (60.2% logic, 39.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.344ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.353ns (60.2% logic, 39.8% route), 9 logic levels. Constraint Details: 15.353ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.344ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.353 (60.2% logic, 39.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.355ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.342ns (62.1% logic, 37.9% route), 10 logic levels. Constraint Details: 15.342ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.355ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.342 (62.1% logic, 37.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.357ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.340ns (62.6% logic, 37.4% route), 11 logic levels. Constraint Details: 15.340ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.357ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.340 (62.6% logic, 37.4% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.358ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.339ns (63.1% logic, 36.9% route), 11 logic levels. Constraint Details: 15.339ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.358ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.339 (63.1% logic, 36.9% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.359ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.338ns (63.2% logic, 36.8% route), 12 logic levels. Constraint Details: 15.338ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.359ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.338 (63.2% logic, 36.8% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.360ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.337ns (61.2% logic, 38.8% route), 9 logic levels. Constraint Details: 15.337ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.360ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOFCO_D --- 0.146 R3C9C.FCI to R3C9C.FCO DDS_inst/SLICE_43 ROUTE 1 0.000 R3C9C.FCO to R3C9D.FCI DDS_inst/mco_10 FCITOF0_DE --- 0.517 R3C9D.FCI to R3C9D.F0 DDS_inst/SLICE_42 ROUTE 1 1.223 R3C9D.F0 to R4C9D.A0 DDS_inst/mult_8u_8u_0_pp_3_11 C0TOFCO_DE --- 0.905 R4C9D.A0 to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF0_DE --- 0.517 R4C10A.FCI to R4C10A.F0 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F0 to R4C8B.A0 DDS_inst/s_mult_8u_8u_0_1_13 C0TOFCO_DE --- 0.905 R4C8B.A0 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.337 (61.2% logic, 38.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.360ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.337ns (61.2% logic, 38.8% route), 9 logic levels. Constraint Details: 15.337ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.360ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOF0_DE --- 0.517 R3C9C.FCI to R3C9C.F0 DDS_inst/SLICE_43 ROUTE 1 1.223 R3C9C.F0 to R4C9C.A0 DDS_inst/mult_8u_8u_0_pp_3_9 C0TOFCO_DE --- 0.905 R4C9C.A0 to R4C9C.FCO DDS_inst/SLICE_6 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI DDS_inst/co_mult_8u_8u_0_1_3 FCITOFCO_D --- 0.146 R4C9D.FCI to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF0_DE --- 0.517 R4C10A.FCI to R4C10A.F0 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F0 to R4C8B.A0 DDS_inst/s_mult_8u_8u_0_1_13 C0TOFCO_DE --- 0.905 R4C8B.A0 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.337 (61.2% logic, 38.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.366ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.331ns (62.3% logic, 37.7% route), 11 logic levels. Constraint Details: 15.331ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.366ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.331 (62.3% logic, 37.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.366ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.331ns (62.3% logic, 37.7% route), 11 logic levels. Constraint Details: 15.331ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.366ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.331 (62.3% logic, 37.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.373ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.324ns (60.3% logic, 39.7% route), 9 logic levels. Constraint Details: 15.324ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.373ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.324 (60.3% logic, 39.7% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.375ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.322ns (62.4% logic, 37.6% route), 12 logic levels. Constraint Details: 15.322ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.375ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.322 (62.4% logic, 37.6% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.317ns (61.4% logic, 38.6% route), 10 logic levels. Constraint Details: 15.317ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.380ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.317 (61.4% logic, 38.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.381ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.316ns (63.3% logic, 36.7% route), 12 logic levels. Constraint Details: 15.316ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.381ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.316 (63.3% logic, 36.7% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.384ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.313ns (61.6% logic, 38.4% route), 9 logic levels. Constraint Details: 15.313ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.384ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.313 (61.6% logic, 38.4% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.387ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.310ns (62.4% logic, 37.6% route), 11 logic levels. Constraint Details: 15.310ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.387ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.310 (62.4% logic, 37.6% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.396ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.301ns (60.9% logic, 39.1% route), 9 logic levels. Constraint Details: 15.301ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.396ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOF0_DE --- 0.517 R3C9C.FCI to R3C9C.F0 DDS_inst/SLICE_43 ROUTE 1 1.223 R3C9C.F0 to R4C9C.A0 DDS_inst/mult_8u_8u_0_pp_3_9 C0TOFCO_DE --- 0.905 R4C9C.A0 to R4C9C.FCO DDS_inst/SLICE_6 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI DDS_inst/co_mult_8u_8u_0_1_3 FCITOF1_DE --- 0.569 R4C9D.FCI to R4C9D.F1 DDS_inst/SLICE_5 ROUTE 1 1.254 R4C9D.F1 to R4C8A.B1 DDS_inst/s_mult_8u_8u_0_1_12 C1TOFCO_DE --- 0.786 R4C8A.B1 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.301 (60.9% logic, 39.1% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.396ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.301ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.301ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.396ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.301 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.396ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.301ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.301ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.396ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.301 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.396ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.301ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.301ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.396ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.301 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.398ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.299ns (62.8% logic, 37.2% route), 11 logic levels. Constraint Details: 15.299ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.398ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.299 (62.8% logic, 37.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.400ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.297ns (60.3% logic, 39.7% route), 8 logic levels. Constraint Details: 15.297ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.400ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.297 (60.3% logic, 39.7% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.402ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.295ns (62.4% logic, 37.6% route), 11 logic levels. Constraint Details: 15.295ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.402ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.295 (62.4% logic, 37.6% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.402ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.295ns (62.4% logic, 37.6% route), 11 logic levels. Constraint Details: 15.295ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.402ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.295 (62.4% logic, 37.6% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.409ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.288ns (62.5% logic, 37.5% route), 11 logic levels. Constraint Details: 15.288ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.409ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.288 (62.5% logic, 37.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.411ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.286ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.286ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.411ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.286 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.411ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.286ns (60.1% logic, 39.9% route), 9 logic levels. Constraint Details: 15.286ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.411ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.286 (60.1% logic, 39.9% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.422ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.275ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.275ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.422ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.275 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.424ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.273ns (62.5% logic, 37.5% route), 11 logic levels. Constraint Details: 15.273ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.424ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.273 (62.5% logic, 37.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.425ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.272ns (62.7% logic, 37.3% route), 10 logic levels. Constraint Details: 15.272ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.425ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.272 (62.7% logic, 37.3% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.425ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.272ns (62.9% logic, 37.1% route), 11 logic levels. Constraint Details: 15.272ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.425ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.272 (62.9% logic, 37.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.426ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.271ns (63.1% logic, 36.9% route), 12 logic levels. Constraint Details: 15.271ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.426ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.271 (63.1% logic, 36.9% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.426ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.271ns (63.1% logic, 36.9% route), 12 logic levels. Constraint Details: 15.271ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.426ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.271 (63.1% logic, 36.9% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.427ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.270ns (61.0% logic, 39.0% route), 9 logic levels. Constraint Details: 15.270ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.427ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOF0_DE --- 0.517 R3C9C.FCI to R3C9C.F0 DDS_inst/SLICE_43 ROUTE 1 1.223 R3C9C.F0 to R4C9C.A0 DDS_inst/mult_8u_8u_0_pp_3_9 C0TOFCO_DE --- 0.905 R4C9C.A0 to R4C9C.FCO DDS_inst/SLICE_6 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI DDS_inst/co_mult_8u_8u_0_1_3 FCITOFCO_D --- 0.146 R4C9D.FCI to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF1_DE --- 0.569 R4C10A.FCI to R4C10A.F1 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F1 to R4C8B.A1 DDS_inst/s_mult_8u_8u_0_1_14 C1TOFCO_DE --- 0.786 R4C8B.A1 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.270 (61.0% logic, 39.0% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.427ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.270ns (61.0% logic, 39.0% route), 9 logic levels. Constraint Details: 15.270ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.427ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOFCO_D --- 0.146 R3C9C.FCI to R3C9C.FCO DDS_inst/SLICE_43 ROUTE 1 0.000 R3C9C.FCO to R3C9D.FCI DDS_inst/mco_10 FCITOF1_DE --- 0.569 R3C9D.FCI to R3C9D.F1 DDS_inst/SLICE_42 ROUTE 1 1.223 R3C9D.F1 to R4C9D.A1 DDS_inst/mult_8u_8u_0_pp_3_12 C1TOFCO_DE --- 0.786 R4C9D.A1 to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF0_DE --- 0.517 R4C10A.FCI to R4C10A.F0 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F0 to R4C8B.A0 DDS_inst/s_mult_8u_8u_0_1_13 C0TOFCO_DE --- 0.905 R4C8B.A0 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.270 (61.0% logic, 39.0% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.427ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.270ns (61.0% logic, 39.0% route), 9 logic levels. Constraint Details: 15.270ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.427ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOFCO_D --- 0.146 R3C9C.FCI to R3C9C.FCO DDS_inst/SLICE_43 ROUTE 1 0.000 R3C9C.FCO to R3C9D.FCI DDS_inst/mco_10 FCITOF0_DE --- 0.517 R3C9D.FCI to R3C9D.F0 DDS_inst/SLICE_42 ROUTE 1 1.223 R3C9D.F0 to R4C9D.A0 DDS_inst/mult_8u_8u_0_pp_3_11 C0TOFCO_DE --- 0.905 R4C9D.A0 to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF1_DE --- 0.569 R4C10A.FCI to R4C10A.F1 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F1 to R4C8B.A1 DDS_inst/s_mult_8u_8u_0_1_14 C1TOFCO_DE --- 0.786 R4C8B.A1 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.270 (61.0% logic, 39.0% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.264ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.264ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.433ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.264 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.264ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.264ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.433ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.264 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.433ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.264ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.264ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.433ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.264 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.436ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.261ns (61.5% logic, 38.5% route), 9 logic levels. Constraint Details: 15.261ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.436ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.261 (61.5% logic, 38.5% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.448ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.249ns (63.2% logic, 36.8% route), 12 logic levels. Constraint Details: 15.249ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.448ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.249 (63.2% logic, 36.8% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.449ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.248ns (61.9% logic, 38.1% route), 9 logic levels. Constraint Details: 15.248ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.449ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.248 (61.9% logic, 38.1% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.452ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.245ns (62.8% logic, 37.2% route), 10 logic levels. Constraint Details: 15.245ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.452ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.245 (62.8% logic, 37.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.452ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.245ns (60.1% logic, 39.9% route), 8 logic levels. Constraint Details: 15.245ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.452ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.245 (60.1% logic, 39.9% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.453ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.244ns (63.0% logic, 37.0% route), 11 logic levels. Constraint Details: 15.244ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.453ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.244 (63.0% logic, 37.0% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.454ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.243ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.243ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.454ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.243 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.454ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.243ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.243ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.454ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.243 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.460ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.237ns (62.1% logic, 37.9% route), 10 logic levels. Constraint Details: 15.237ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.460ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.237 (62.1% logic, 37.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.460ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.237ns (62.1% logic, 37.9% route), 10 logic levels. Constraint Details: 15.237ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.460ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.237 (62.1% logic, 37.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.463ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.234ns (63.5% logic, 36.5% route), 11 logic levels. Constraint Details: 15.234ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.463ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.234 (63.5% logic, 36.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.463ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.234ns (59.9% logic, 40.1% route), 9 logic levels. Constraint Details: 15.234ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.463ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.234 (59.9% logic, 40.1% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.463ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.234ns (59.9% logic, 40.1% route), 9 logic levels. Constraint Details: 15.234ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.463ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.234 (59.9% logic, 40.1% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.467ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.230ns (60.1% logic, 39.9% route), 8 logic levels. Constraint Details: 15.230ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.467ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.230 (60.1% logic, 39.9% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.469ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.228ns (62.2% logic, 37.8% route), 11 logic levels. Constraint Details: 15.228ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.469ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.228 (62.2% logic, 37.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.475ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.222ns (63.1% logic, 36.9% route), 11 logic levels. Constraint Details: 15.222ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.475ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.222 (63.1% logic, 36.9% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.476ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.221ns (62.3% logic, 37.7% route), 11 logic levels. Constraint Details: 15.221ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.476ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.221 (62.3% logic, 37.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.477ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.220ns (62.6% logic, 37.4% route), 10 logic levels. Constraint Details: 15.220ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.477ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.220 (62.6% logic, 37.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.479ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.218ns (62.8% logic, 37.2% route), 11 logic levels. Constraint Details: 15.218ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.479ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.542 R7C9C.F1 to R3C7B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R3C7B.C1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.218 (62.8% logic, 37.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.481ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.216ns (62.2% logic, 37.8% route), 10 logic levels. Constraint Details: 15.216ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.481ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.216 (62.2% logic, 37.8% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.489ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.208ns (62.2% logic, 37.8% route), 10 logic levels. Constraint Details: 15.208ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.489ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.208 (62.2% logic, 37.8% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.490ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.207ns (60.6% logic, 39.4% route), 8 logic levels. Constraint Details: 15.207ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.490ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOF0_DE --- 0.517 R3C9C.FCI to R3C9C.F0 DDS_inst/SLICE_43 ROUTE 1 1.223 R3C9C.F0 to R4C9C.A0 DDS_inst/mult_8u_8u_0_pp_3_9 C0TOFCO_DE --- 0.905 R4C9C.A0 to R4C9C.FCO DDS_inst/SLICE_6 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI DDS_inst/co_mult_8u_8u_0_1_3 FCITOF1_DE --- 0.569 R4C9D.FCI to R4C9D.F1 DDS_inst/SLICE_5 ROUTE 1 1.254 R4C9D.F1 to R4C8A.B1 DDS_inst/s_mult_8u_8u_0_1_12 C1TOFCO_DE --- 0.786 R4C8A.B1 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.207 (60.6% logic, 39.4% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.490ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.207ns (63.6% logic, 36.4% route), 11 logic levels. Constraint Details: 15.207ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.490ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.207 (63.6% logic, 36.4% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.492ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.205ns (62.6% logic, 37.4% route), 10 logic levels. Constraint Details: 15.205ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.492ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.205 (62.6% logic, 37.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.493ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.204ns (62.9% logic, 37.1% route), 12 logic levels. Constraint Details: 15.204ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.493ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.204 (62.9% logic, 37.1% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.494ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.203ns (60.8% logic, 39.2% route), 9 logic levels. Constraint Details: 15.203ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.494ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOFCO_D --- 0.146 R3C9C.FCI to R3C9C.FCO DDS_inst/SLICE_43 ROUTE 1 0.000 R3C9C.FCO to R3C9D.FCI DDS_inst/mco_10 FCITOF1_DE --- 0.569 R3C9D.FCI to R3C9D.F1 DDS_inst/SLICE_42 ROUTE 1 1.223 R3C9D.F1 to R4C9D.A1 DDS_inst/mult_8u_8u_0_pp_3_12 C1TOFCO_DE --- 0.786 R4C9D.A1 to R4C9D.FCO DDS_inst/SLICE_5 ROUTE 1 0.000 R4C9D.FCO to R4C10A.FCI DDS_inst/co_mult_8u_8u_0_1_4 FCITOF1_DE --- 0.569 R4C10A.FCI to R4C10A.F1 DDS_inst/SLICE_56 ROUTE 1 1.223 R4C10A.F1 to R4C8B.A1 DDS_inst/s_mult_8u_8u_0_1_14 C1TOFCO_DE --- 0.786 R4C8B.A1 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.203 (60.8% logic, 39.2% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.501ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.196ns (61.7% logic, 38.3% route), 9 logic levels. Constraint Details: 15.196ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.501ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.196 (61.7% logic, 38.3% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.503ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.194ns (62.3% logic, 37.7% route), 10 logic levels. Constraint Details: 15.194ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.503ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.194 (62.3% logic, 37.7% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.504ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.193ns (62.7% logic, 37.3% route), 10 logic levels. Constraint Details: 15.193ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.504ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.193 (62.7% logic, 37.3% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.505ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.192ns (62.9% logic, 37.1% route), 11 logic levels. Constraint Details: 15.192ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.505ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.192 (62.9% logic, 37.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.512ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.185ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.185ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.512ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.185 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.512ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.185ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.185ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.512ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.185 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.516ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.181ns (61.7% logic, 38.3% route), 9 logic levels. Constraint Details: 15.181ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.516ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.181 (61.7% logic, 38.3% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.519ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.178ns (62.7% logic, 37.3% route), 10 logic levels. Constraint Details: 15.178ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.519ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.178 (62.7% logic, 37.3% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.519ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.178ns (60.0% logic, 40.0% route), 8 logic levels. Constraint Details: 15.178ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.519ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.178 (60.0% logic, 40.0% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.520ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.177ns (62.9% logic, 37.1% route), 11 logic levels. Constraint Details: 15.177ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.520ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.177 (62.9% logic, 37.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.520ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.177ns (62.9% logic, 37.1% route), 11 logic levels. Constraint Details: 15.177ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.520ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.177 (62.9% logic, 37.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.521ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.176ns (62.1% logic, 37.9% route), 11 logic levels. Constraint Details: 15.176ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.521ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.176 (62.1% logic, 37.9% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.522ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.175ns (63.0% logic, 37.0% route), 11 logic levels. Constraint Details: 15.175ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.522ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOFCO_D --- 0.146 R5C8B.FCI to R5C8B.FCO DDS_inst/SLICE_12 ROUTE 1 0.000 R5C8B.FCO to R5C8C.FCI DDS_inst/co_mult_8u_8u_0_0_6 FCITOF0_DE --- 0.517 R5C8C.FCI to R5C8C.F0 DDS_inst/SLICE_11 ROUTE 1 0.563 R5C8C.F0 to R4C8B.D0 DDS_inst/s_mult_8u_8u_0_0_13 C0TOFCO_DE --- 0.905 R4C8B.D0 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.175 (63.0% logic, 37.0% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.527ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.170ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.170ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.527ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.170 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.527ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.170ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.170ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.527ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.170 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.527ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.170ns (63.0% logic, 37.0% route), 11 logic levels. Constraint Details: 15.170ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.527ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.170 (63.0% logic, 37.0% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.527ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.170ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.170ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.527ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.170 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.530ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.167ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.167ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.530ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.167 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.530ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.167ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.167ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.530ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.167 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.530ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.167ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.167ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.530ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.167 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.533ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.164ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.164ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.533ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.164 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.539ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.158ns (64.0% logic, 36.0% route), 12 logic levels. Constraint Details: 15.158ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.539ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOFCO_D --- 0.146 R5C6A.FCI to R5C6A.FCO DDS_inst/SLICE_53 ROUTE 1 0.000 R5C6A.FCO to R5C6B.FCI DDS_inst/mfco FCITOF0_DE --- 0.517 R5C6B.FCI to R5C6B.F0 DDS_inst/SLICE_37 ROUTE 1 0.904 R5C6B.F0 to R5C8A.B0 DDS_inst/mult_8u_8u_0_pp_0_9 C0TOFCO_DE --- 0.905 R5C8A.B0 to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.158 (64.0% logic, 36.0% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.539ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.158ns (64.0% logic, 36.0% route), 12 logic levels. Constraint Details: 15.158ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.539ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOF0_DE --- 0.517 R5C7C.FCI to R5C7C.F0 DDS_inst/SLICE_15 ROUTE 1 0.882 R5C7C.F0 to R4C7B.B0 DDS_inst/s_mult_8u_8u_0_0_5 C0TOFCO_DE --- 0.905 R4C7B.B0 to R4C7B.FCO DDS_inst/SLICE_25 ROUTE 1 0.000 R4C7B.FCO to R4C7C.FCI DDS_inst/co_t_mult_8u_8u_0_2_2 FCITOFCO_D --- 0.146 R4C7C.FCI to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.158 (64.0% logic, 36.0% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.542ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.155ns (62.9% logic, 37.1% route), 11 logic levels. Constraint Details: 15.155ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.542ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.155 (62.9% logic, 37.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.542ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.155ns (60.5% logic, 39.5% route), 8 logic levels. Constraint Details: 15.155ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.542ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 2.349 R5C8D.F0 to R3C9B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C9B.A0 to R3C9B.FCO DDS_inst/SLICE_44 ROUTE 1 0.000 R3C9B.FCO to R3C9C.FCI DDS_inst/mco_9 FCITOF0_DE --- 0.517 R3C9C.FCI to R3C9C.F0 DDS_inst/SLICE_43 ROUTE 1 1.223 R3C9C.F0 to R4C9C.A0 DDS_inst/mult_8u_8u_0_pp_3_9 C0TOFCO_DE --- 0.905 R4C9C.A0 to R4C9C.FCO DDS_inst/SLICE_6 ROUTE 1 0.000 R4C9C.FCO to R4C9D.FCI DDS_inst/co_mult_8u_8u_0_1_3 FCITOF1_DE --- 0.569 R4C9D.FCI to R4C9D.F1 DDS_inst/SLICE_5 ROUTE 1 1.254 R4C9D.F1 to R4C8A.B1 DDS_inst/s_mult_8u_8u_0_1_12 C1TOFCO_DE --- 0.786 R4C8A.B1 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.155 (60.5% logic, 39.5% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.544ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.153ns (62.4% logic, 37.6% route), 10 logic levels. Constraint Details: 15.153ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.544ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.153 (62.4% logic, 37.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.546ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.151ns (62.6% logic, 37.4% route), 11 logic levels. Constraint Details: 15.151ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.546ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.542 R7C9C.F1 to R3C7B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R3C7B.C1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.151 (62.6% logic, 37.4% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.548ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.149ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.149ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.548ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.149 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.548ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.149ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.149ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.548ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.149 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.551ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.146ns (64.0% logic, 36.0% route), 12 logic levels. Constraint Details: 15.146ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.551ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOF0_DE --- 0.517 R5C5D.FCI to R5C5D.F0 DDS_inst/SLICE_23 ROUTE 1 0.563 R5C5D.F0 to R5C7C.D0 DDS_inst/mult_8u_8u_0_pp_0_5 C0TOFCO_DE --- 0.905 R5C7C.D0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.146 (64.0% logic, 36.0% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.555ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.142ns (62.1% logic, 37.9% route), 10 logic levels. Constraint Details: 15.142ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.555ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.142 (62.1% logic, 37.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.557ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.140ns (63.5% logic, 36.5% route), 11 logic levels. Constraint Details: 15.140ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.557ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.140 (63.5% logic, 36.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.557ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.140ns (63.5% logic, 36.5% route), 11 logic levels. Constraint Details: 15.140ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.557ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.140 (63.5% logic, 36.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.557ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.140ns (63.3% logic, 36.7% route), 10 logic levels. Constraint Details: 15.140ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.557ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.140 (63.3% logic, 36.7% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.557ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.140ns (63.5% logic, 36.5% route), 11 logic levels. Constraint Details: 15.140ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.557ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.140 (63.5% logic, 36.5% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.563ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.134ns (63.9% logic, 36.1% route), 11 logic levels. Constraint Details: 15.134ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.563ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.843 R7C9C.F1 to R5C5C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R5C5C.A0 to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.134 (63.9% logic, 36.1% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.568ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.129ns (61.6% logic, 38.4% route), 9 logic levels. Constraint Details: 15.129ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.568ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.129 (61.6% logic, 38.4% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.570ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.127ns (64.1% logic, 35.9% route), 12 logic levels. Constraint Details: 15.127ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.570ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.127 (64.1% logic, 35.9% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.570ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.127ns (64.1% logic, 35.9% route), 12 logic levels. Constraint Details: 15.127ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.570ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.127 (64.1% logic, 35.9% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.570ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.127ns (62.1% logic, 37.9% route), 10 logic levels. Constraint Details: 15.127ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.570ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.127 (62.1% logic, 37.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.571ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.126ns (62.4% logic, 37.6% route), 9 logic levels. Constraint Details: 15.126ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.571ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.126 (62.4% logic, 37.6% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.571ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.126ns (62.5% logic, 37.5% route), 10 logic levels. Constraint Details: 15.126ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.571ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.126 (62.5% logic, 37.5% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.125ns (62.7% logic, 37.3% route), 11 logic levels. Constraint Details: 15.125ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.572ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.125 (62.7% logic, 37.3% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.572ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.125ns (62.7% logic, 37.3% route), 11 logic levels. Constraint Details: 15.125ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.572ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.125 (62.7% logic, 37.3% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.573ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.124ns (62.6% logic, 37.4% route), 10 logic levels. Constraint Details: 15.124ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.573ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.542 R7C9C.F1 to R3C7B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R3C7B.C1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.124 (62.6% logic, 37.4% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.578ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.119ns (63.0% logic, 37.0% route), 10 logic levels. Constraint Details: 15.119ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.578ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOFCO_D --- 0.146 R5C8B.FCI to R5C8B.FCO DDS_inst/SLICE_12 ROUTE 1 0.000 R5C8B.FCO to R5C8C.FCI DDS_inst/co_mult_8u_8u_0_0_6 FCITOF0_DE --- 0.517 R5C8C.FCI to R5C8C.F0 DDS_inst/SLICE_11 ROUTE 1 0.563 R5C8C.F0 to R4C8B.D0 DDS_inst/s_mult_8u_8u_0_0_13 C0TOFCO_DE --- 0.905 R4C8B.D0 to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.119 (63.0% logic, 37.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.118ns (61.8% logic, 38.2% route), 10 logic levels. Constraint Details: 15.118ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.579ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.118 (61.8% logic, 38.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.118ns (61.8% logic, 38.2% route), 10 logic levels. Constraint Details: 15.118ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.579ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.118 (61.8% logic, 38.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.579ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.118ns (61.8% logic, 38.2% route), 10 logic levels. Constraint Details: 15.118ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.579ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.118 (61.8% logic, 38.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.583ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.114ns (62.0% logic, 38.0% route), 9 logic levels. Constraint Details: 15.114ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.583ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 2.087 R7C9C.F1 to R3C7C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R3C7C.A0 to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.114 (62.0% logic, 38.0% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.584ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.113ns (63.4% logic, 36.6% route), 10 logic levels. Constraint Details: 15.113ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.584ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.113 (63.4% logic, 36.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.587ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.110ns (62.7% logic, 37.3% route), 11 logic levels. Constraint Details: 15.110ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.587ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.110 (62.7% logic, 37.3% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.589ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.108ns (62.8% logic, 37.2% route), 11 logic levels. Constraint Details: 15.108ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.589ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF1_DE --- 0.569 R5C8B.FCI to R5C8B.F1 DDS_inst/SLICE_12 ROUTE 1 0.563 R5C8B.F1 to R4C8A.D1 DDS_inst/s_mult_8u_8u_0_0_12 C1TOFCO_DE --- 0.786 R4C8A.D1 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.108 (62.8% logic, 37.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.592ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.105ns (64.2% logic, 35.8% route), 12 logic levels. Constraint Details: 15.105ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.592ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOFCO_D --- 0.146 R5C8A.FCI to R5C8A.FCO DDS_inst/SLICE_13 ROUTE 1 0.000 R5C8A.FCO to R5C8B.FCI DDS_inst/co_mult_8u_8u_0_0_5 FCITOF0_DE --- 0.517 R5C8B.FCI to R5C8B.F0 DDS_inst/SLICE_12 ROUTE 1 0.851 R5C8B.F0 to R4C8A.A0 DDS_inst/s_mult_8u_8u_0_0_11 C0TOFCO_DE --- 0.905 R4C8A.A0 to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.105 (64.2% logic, 35.8% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.594ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.103ns (62.8% logic, 37.2% route), 11 logic levels. Constraint Details: 15.103ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.594ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.103 (62.8% logic, 37.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.595ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.102ns (61.5% logic, 38.5% route), 8 logic levels. Constraint Details: 15.102ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.595ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO5 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.437 EBR_R6C7.DO5 to R7C7C.B0 DDS_inst/ROM_inst/n287 CTOF_DEL --- 0.452 R7C7C.B0 to R7C7C.F0 DDS_inst/SLICE_227 ROUTE 8 2.346 R7C7C.F0 to R5C5D.C0 DDS_inst/DataFromROM_5 C0TOFCO_DE --- 0.905 R5C5D.C0 to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.102 (61.5% logic, 38.5% route), 8 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.100ns (63.2% logic, 36.8% route), 11 logic levels. Constraint Details: 15.100ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.597ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.100 (63.2% logic, 36.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.597ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.100ns (63.2% logic, 36.8% route), 11 logic levels. Constraint Details: 15.100ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.597ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.100 (63.2% logic, 36.8% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.598ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.099ns (62.5% logic, 37.5% route), 9 logic levels. Constraint Details: 15.099ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.598ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.099 (62.5% logic, 37.5% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.599ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.098ns (62.7% logic, 37.3% route), 10 logic levels. Constraint Details: 15.098ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.599ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.098 (62.7% logic, 37.3% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.600ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.097ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.097ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.600ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF0_DE --- 0.517 R5C5C.FCI to R5C5C.F0 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F0 to R5C7B.A0 DDS_inst/mult_8u_8u_0_pp_0_3 C0TOFCO_DE --- 0.905 R5C7B.A0 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.097 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.600ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.097ns (61.9% logic, 38.1% route), 10 logic levels. Constraint Details: 15.097ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.600ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.097 (61.9% logic, 38.1% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.606ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.091ns (63.8% logic, 36.2% route), 12 logic levels. Constraint Details: 15.091ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.606ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOF0_DE --- 0.517 R5C7C.FCI to R5C7C.F0 DDS_inst/SLICE_15 ROUTE 1 0.882 R5C7C.F0 to R4C7B.B0 DDS_inst/s_mult_8u_8u_0_0_5 C0TOFCO_DE --- 0.905 R4C7B.B0 to R4C7B.FCO DDS_inst/SLICE_25 ROUTE 1 0.000 R4C7B.FCO to R4C7C.FCI DDS_inst/co_t_mult_8u_8u_0_2_2 FCITOFCO_D --- 0.146 R4C7C.FCI to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.091 (63.8% logic, 36.2% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.606ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.091ns (61.7% logic, 38.3% route), 9 logic levels. Constraint Details: 15.091ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.606ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R3C7B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R3C7B.A1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOF0_DE --- 0.517 R5C7D.FCI to R5C7D.F0 DDS_inst/SLICE_14 ROUTE 1 0.851 R5C7D.F0 to R4C7C.A0 DDS_inst/s_mult_8u_8u_0_0_7 C0TOFCO_DE --- 0.905 R4C7C.A0 to R4C7C.FCO DDS_inst/SLICE_24 ROUTE 1 0.000 R4C7C.FCO to R4C7D.FCI DDS_inst/co_t_mult_8u_8u_0_2_3 FCITOFCO_D --- 0.146 R4C7D.FCI to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.091 (61.7% logic, 38.3% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.609ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.088ns (63.1% logic, 36.9% route), 10 logic levels. Constraint Details: 15.088ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.609ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.088 (63.1% logic, 36.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.611ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.086ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.086ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.611ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.542 R7C9C.F1 to R3C7B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R3C7B.C1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.086 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.615ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.082ns (61.8% logic, 38.2% route), 10 logic levels. Constraint Details: 15.082ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.615ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOF1_DE --- 0.569 R5C5C.FCI to R5C5C.F1 DDS_inst/SLICE_0 ROUTE 1 0.873 R5C5C.F1 to R5C7B.A1 DDS_inst/mult_8u_8u_0_pp_0_4 C1TOFCO_DE --- 0.786 R5C7B.A1 to R5C7B.FCO DDS_inst/SLICE_16 ROUTE 1 0.000 R5C7B.FCO to R5C7C.FCI DDS_inst/co_mult_8u_8u_0_0_2 FCITOFCO_D --- 0.146 R5C7C.FCI to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.082 (61.8% logic, 38.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.618ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.079ns (63.9% logic, 36.1% route), 12 logic levels. Constraint Details: 15.079ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.618ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOF0_DE --- 0.517 R5C5D.FCI to R5C5D.F0 DDS_inst/SLICE_23 ROUTE 1 0.563 R5C5D.F0 to R5C7C.D0 DDS_inst/mult_8u_8u_0_pp_0_5 C0TOFCO_DE --- 0.905 R5C7C.D0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.079 (63.9% logic, 36.1% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.618ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.079ns (63.9% logic, 36.1% route), 12 logic levels. Constraint Details: 15.079ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.618ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOF1_DE --- 0.569 R5C5D.FCI to R5C5D.F1 DDS_inst/SLICE_23 ROUTE 1 0.563 R5C5D.F1 to R5C7C.D1 DDS_inst/mult_8u_8u_0_pp_0_6 C1TOFCO_DE --- 0.786 R5C7C.D1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.079 (63.9% logic, 36.1% route), 12 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.621ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i5 (to Clock_c +) Delay: 15.076ns (62.8% logic, 37.2% route), 10 logic levels. Constraint Details: 15.076ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.621ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.998 R7C9C.F1 to R5C5B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R5C5B.C1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF1_DE --- 0.569 R4C8A.FCI to R4C8A.F1 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F1 to R4C8A.DI1 DDS_inst/Signal_o_7_N_80_12 (to Clock_c) -------- 15.076 (62.8% logic, 37.2% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.622ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.075ns (62.0% logic, 38.0% route), 10 logic levels. Constraint Details: 15.075ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.622ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 2.457 R7C9D.F1 to R5C5B.A1 DDS_inst/DataFromROM_1 C1TOFCO_DE --- 0.786 R5C5B.A1 to R5C5B.FCO DDS_inst/SLICE_1 ROUTE 1 0.000 R5C5B.FCO to R5C5C.FCI DDS_inst/mco FCITOFCO_D --- 0.146 R5C5C.FCI to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.075 (62.0% logic, 38.0% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.623ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i4 (to Clock_c +) Delay: 15.074ns (62.2% logic, 37.8% route), 9 logic levels. Constraint Details: 15.074ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.623ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOF0_DE --- 0.517 R4C8A.FCI to R4C8A.F0 DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.F0 to R4C8A.DI0 DDS_inst/Signal_o_7_N_80_11 (to Clock_c) -------- 15.074 (62.2% logic, 37.8% route), 9 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_4: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.624ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.073ns (63.1% logic, 36.9% route), 10 logic levels. Constraint Details: 15.073ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.624ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.073 (63.1% logic, 36.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.624ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.073ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.073ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.624ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.073 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.624ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.073ns (63.1% logic, 36.9% route), 10 logic levels. Constraint Details: 15.073ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.624ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF0_DE --- 0.517 R3C7C.FCI to R3C7C.F0 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F0 to R5C7C.A0 DDS_inst/mult_8u_8u_0_pp_1_5 C0TOFCO_DE --- 0.905 R5C7C.A0 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.073 (63.1% logic, 36.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.624ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i7 (to Clock_c +) Delay: 15.073ns (63.1% logic, 36.9% route), 10 logic levels. Constraint Details: 15.073ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.624ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO1 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.245 EBR_R6C7.DO1 to R7C9D.D1 DDS_inst/ROM_inst/n291 CTOF_DEL --- 0.452 R7C9D.D1 to R7C9D.F1 DDS_inst/SLICE_225 ROUTE 8 1.912 R7C9D.F1 to R3C7B.C0 DDS_inst/DataFromROM_1 C0TOFCO_DE --- 0.905 R3C7B.C0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOF1_DE --- 0.569 R3C7C.FCI to R3C7C.F1 DDS_inst/SLICE_51 ROUTE 1 1.223 R3C7C.F1 to R5C7C.A1 DDS_inst/mult_8u_8u_0_pp_1_6 C1TOFCO_DE --- 0.786 R5C7C.A1 to R5C7C.FCO DDS_inst/SLICE_15 ROUTE 1 0.000 R5C7C.FCO to R5C7D.FCI DDS_inst/co_mult_8u_8u_0_0_3 FCITOFCO_D --- 0.146 R5C7D.FCI to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF1_DE --- 0.569 R4C8B.FCI to R4C8B.F1 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F1 to R4C8B.DI1 DDS_inst/Signal_o_7_N_80_14 (to Clock_c) -------- 15.073 (63.1% logic, 36.9% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.624ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.073ns (63.3% logic, 36.7% route), 11 logic levels. Constraint Details: 15.073ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.624ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO0 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 4 1.160 EBR_R6C7.DO0 to R5C8D.C0 DDS_inst/ROM_inst/n292 CTOF_DEL --- 0.452 R5C8D.C0 to R5C8D.F0 DDS_inst/SLICE_221 ROUTE 4 1.970 R5C8D.F0 to R3C7B.A0 DDS_inst/DataFromROM_0 C0TOFCO_DE --- 0.905 R3C7B.A0 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF1_DE --- 0.569 R3C7D.FCI to R3C7D.F1 DDS_inst/SLICE_50 ROUTE 1 1.223 R3C7D.F1 to R5C7D.A1 DDS_inst/mult_8u_8u_0_pp_1_8 C1TOFCO_DE --- 0.786 R5C7D.A1 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.073 (63.3% logic, 36.7% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.625ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i6 (to Clock_c +) Delay: 15.072ns (62.4% logic, 37.6% route), 10 logic levels. Constraint Details: 15.072ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.625ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.542 R7C9C.F1 to R3C7B.C1 DDS_inst/DataFromROM_2 C1TOFCO_DE --- 0.786 R3C7B.C1 to R3C7B.FCO DDS_inst/SLICE_52 ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI DDS_inst/mco_3 FCITOFCO_D --- 0.146 R3C7C.FCI to R3C7C.FCO DDS_inst/SLICE_51 ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI DDS_inst/mco_4 FCITOF0_DE --- 0.517 R3C7D.FCI to R3C7D.F0 DDS_inst/SLICE_50 ROUTE 1 1.355 R3C7D.F0 to R5C7D.B0 DDS_inst/mult_8u_8u_0_pp_1_7 C0TOFCO_DE --- 0.905 R5C7D.B0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF0_DE --- 0.517 R5C8A.FCI to R5C8A.F0 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F0 to R4C7D.B0 DDS_inst/s_mult_8u_8u_0_0_9 C0TOFCO_DE --- 0.905 R4C7D.B0 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOF0_DE --- 0.517 R4C8B.FCI to R4C8B.F0 DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.F0 to R4C8B.DI0 DDS_inst/Signal_o_7_N_80_13 (to Clock_c) -------- 15.072 (62.4% logic, 37.6% route), 10 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 24.630ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: SP8KC Port DDS_inst/ROM_inst/mux_134(ASIC) (from Clock_c +) Destination: FF Data in DDS_inst/Temp_i8 (to Clock_c +) Delay: 15.067ns (63.8% logic, 36.2% route), 11 logic levels. Constraint Details: 15.067ns physical path delay DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2 meets 40.000ns delay constraint less 0.153ns skew and 0.150ns DIN_SET requirement (totaling 39.697ns) by 24.630ns Physical Path Details: Data path DDS_inst/ROM_inst/mux_134 to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource C2Q_DEL --- 4.518 EBR_R6C7.CLK to EBR_R6C7.DO2 DDS_inst/ROM_inst/mux_134 (from Clock_c) ROUTE 1 1.586 EBR_R6C7.DO2 to R7C9C.B1 DDS_inst/ROM_inst/n290 CTOF_DEL --- 0.452 R7C9C.B1 to R7C9C.F1 DDS_inst/SLICE_226 ROUTE 8 1.843 R7C9C.F1 to R5C5C.A0 DDS_inst/DataFromROM_2 C0TOFCO_DE --- 0.905 R5C5C.A0 to R5C5C.FCO DDS_inst/SLICE_0 ROUTE 1 0.000 R5C5C.FCO to R5C5D.FCI DDS_inst/mco_1 FCITOFCO_D --- 0.146 R5C5D.FCI to R5C5D.FCO DDS_inst/SLICE_23 ROUTE 1 0.000 R5C5D.FCO to R5C6A.FCI DDS_inst/mco_2 FCITOF0_DE --- 0.517 R5C6A.FCI to R5C6A.F0 DDS_inst/SLICE_53 ROUTE 1 0.851 R5C6A.F0 to R5C7D.A0 DDS_inst/mult_8u_8u_0_pp_0_7 C0TOFCO_DE --- 0.905 R5C7D.A0 to R5C7D.FCO DDS_inst/SLICE_14 ROUTE 1 0.000 R5C7D.FCO to R5C8A.FCI DDS_inst/co_mult_8u_8u_0_0_4 FCITOF1_DE --- 0.569 R5C8A.FCI to R5C8A.F1 DDS_inst/SLICE_13 ROUTE 1 1.180 R5C8A.F1 to R4C7D.B1 DDS_inst/s_mult_8u_8u_0_0_10 C1TOFCO_DE --- 0.786 R4C7D.B1 to R4C7D.FCO DDS_inst/SLICE_7 ROUTE 1 0.000 R4C7D.FCO to R4C8A.FCI DDS_inst/co_t_mult_8u_8u_0_2_4 FCITOFCO_D --- 0.146 R4C8A.FCI to R4C8A.FCO DDS_inst/SLICE_4 ROUTE 1 0.000 R4C8A.FCO to R4C8B.FCI DDS_inst/co_t_mult_8u_8u_0_2_5 FCITOFCO_D --- 0.146 R4C8B.FCI to R4C8B.FCO DDS_inst/SLICE_3 ROUTE 1 0.000 R4C8B.FCO to R4C8C.FCI DDS_inst/co_t_mult_8u_8u_0_2_6 FCITOF0_DE --- 0.517 R4C8C.FCI to R4C8C.F0 DDS_inst/SLICE_2 ROUTE 1 0.000 R4C8C.F0 to R4C8C.DI0 DDS_inst/Signal_o_7_N_80_15 (to Clock_c) -------- 15.067 (63.8% logic, 36.2% route), 11 logic levels. Clock Skew Details: Source Clock Path Clock to DDS_inst/ROM_inst/mux_134: Name Fanout Delay (ns) Site Resource ROUTE 135 2.154 20.PADDI to EBR_R6C7.CLK Clock_c -------- 2.154 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DDS_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 135 2.001 20.PADDI to R4C8C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Report: 62.131MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 25.000 MHz| 62.131 MHz| 11 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 135 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 30733 paths, 1 nets, and 1430 connections (86.35% coverage)