Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.13.0.56.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Sat Mar 30 12:06:51 2024 Command Line: synthesis -f Kurs25_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs25/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Lattice/Kurs25 (searchpath added) -p C:/lscc/diamond/3.13/ispfpga/xo2c00/data (searchpath added) -p C:/Lattice/Kurs25/impl1 (searchpath added) -p C:/Lattice/Kurs25 (searchpath added) Verilog design file = C:/Lattice/Kurs25/impl1/source/decoder_7seg.v Verilog design file = C:/Lattice/Kurs25/impl1/source/dds.v Verilog design file = C:/Lattice/Kurs25/impl1/source/display_multiplex.v Verilog design file = C:/Lattice/Kurs25/impl1/source/double_dabble.v Verilog design file = C:/Lattice/Kurs25/impl1/source/edge_detector.v Verilog design file = C:/Lattice/Kurs25/impl1/source/encoder.v Verilog design file = C:/Lattice/Kurs25/impl1/source/frequency_meter.v Verilog design file = C:/Lattice/Kurs25/impl1/source/rom.v Verilog design file = C:/Lattice/Kurs25/impl1/source/strobe_generator.v Verilog design file = C:/Lattice/Kurs25/impl1/source/synchronizer.v Verilog design file = C:/Lattice/Kurs25/impl1/source/top.v Verilog design file = C:/Lattice/Kurs25/impl1/source/Multiplier.v NGD file = Kurs25_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/lattice/kurs25/impl1/source/decoder_7seg.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/dds.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/display_multiplex.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/double_dabble.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/edge_detector.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/encoder.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/frequency_meter.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/rom.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/strobe_generator.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/synchronizer.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/top.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs25/impl1/source/multiplier.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: c:/lattice/kurs25/impl1/source/top.v(5): compiling module top. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/encoder.v(4): compiling module Encoder. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/synchronizer.v(4): compiling module Synchronizer(WIDTH=3). VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/edge_detector.v(4): compiling module EdgeDetector. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/dds.v(5): compiling module DDS. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/rom.v(4): compiling module ROM(ADDRESS_WIDTH=10,MEMORY_DEPTH=1024,MEMORY_FILE="sin.mem"). VERI-1018 WARNING - synthesis: c:/lattice/kurs25/impl1/source/rom.v(18): net Memory does not have a driver. VDB-1002 INFO - synthesis: c:/lattice/kurs25/impl1/source/multiplier.v(8): compiling module Multiplier. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43): compiling module AND2. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(187): compiling module FD1P3DX. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(138): compiling module FADD2B. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(684): compiling module MULT2. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/frequency_meter.v(5): compiling module FrequencyMeter. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/synchronizer.v(4): compiling module Synchronizer. VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000000). VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/double_dabble.v(5): compiling module DoubleDabble(INPUT_BITS=26,OUTPUT_DIGITS=8). VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/display_multiplex.v(4): compiling module DisplayMultiplex(CLOCK_HZ=25000000). VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000). VERI-1018 INFO - synthesis: c:/lattice/kurs25/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga. Package Status: Final Version 1.44. Top-level module name = top. WARNING - synthesis: c:/lattice/kurs25/impl1/source/rom.v(18): ram Memory_original_ramnet has no write-port on it. VDB-1038 INFO - synthesis: Extracted state machine for register '\EncoderFreq_inst/State' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register '\EncoderAmpl_inst/State' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 GSR instance connected to net Reset_c. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in top_drc.log. Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs25_impl1.ngd. ################### Begin Area Report (top)###################### Number of register bits => 360 of 1520 (23 % ) AND2 => 3 CCU2D => 59 FADD2B => 28 FD1P3AX => 63 FD1P3DX => 124 FD1P3IX => 65 FD1S3AX => 57 FD1S3AY => 10 FD1S3IX => 16 FD1S3JX => 25 GSR => 1 IB => 6 LUT4 => 207 MULT2 => 16 OB => 24 PFUMX => 5 SP8KC => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock_c, loads : 361 Clock Enable Nets Number of Clock Enables: 11 Top 10 highest fanout Clock Enables: Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125, loads : 32 Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_37, loads : 26 Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_10, loads : 3 Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_12, loads : 2 Net : Clock_c_enable_63, loads : 1 Net : EncoderFreq_inst/Clock_c_enable_5, loads : 1 Net : EncoderFreq_inst/Clock_c_enable_6, loads : 1 Net : Clock_c_enable_94, loads : 1 Net : EncoderAmpl_inst/Clock_c_enable_7, loads : 1 Net : EncoderAmpl_inst/Clock_c_enable_1, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : FrequencyMeter_inst/StrobeGenerator_inst/n2255, loads : 49 Net : FrequencyMeter_inst/DoubleDabble_inst/State, loads : 39 Net : FrequencyMeter_inst/StrobeGenerator_inst/n2254, loads : 33 Net : Clock_c_enable_94, loads : 32 Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_125, loads : 32 Net : FrequencyMeter_inst/DisplayMultiplex_inst/TempData_3_N_442_2, loads : 31 Net : FrequencyMeter_inst/StrobeGenerator_inst/Strobe_o_N_225, loads : 28 Net : Clock_c_enable_63, loads : 26 Net : FrequencyMeter_inst/DoubleDabble_inst/Clock_c_enable_37, loads : 26 Net : FrequencyMeter_inst/DisplayMultiplex_inst/TempData_3_N_442_4, loads : 24 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock_c] | 200.000 MHz| 100.110 MHz| 8 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 67.355 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.969 secs --------------------------------------------------------------