Setting log file to 'C:/Lattice/Kurs27/impl1/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
(VERI-1482) Analyzing Verilog file 'C:/Lattice/Kurs27/impl1/source/vga.v'
INFO - C:/Lattice/Kurs27/impl1/source/vga.v(4,8-4,11) (VERI-1018) compiling module 'VGA'
INFO - C:/Lattice/Kurs27/impl1/source/vga.v(4,1-150,10) (VERI-9000) elaborating module 'VGA'
Done: design load finished with (0) errors, and (0) warnings