Lattice Mapping Report File for Design Module 'VGA'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
     Kurs27_impl1.ngd -o Kurs27_impl1_map.ncd -pr Kurs27_impl1.prf -mp
     Kurs27_impl1.mrp -lpf C:/Lattice/Kurs27/impl1/Kurs27_impl1.lpf -lpf
     C:/Lattice/Kurs27/Kurs27.lpf -c 0 -gui 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200HCTQFP100
Target Performance:   5
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.13.0.56.2
Mapped on:  07/04/24  21:07:08


Design Summary
   Number of registers:     33 out of  1520 (2%)
      PFU registers:           33 out of  1280 (3%)
      PIO registers:            0 out of   240 (0%)
   Number of SLICEs:        35 out of   640 (5%)
      SLICEs as Logic/ROM:     35 out of   640 (5%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         12 out of   640 (2%)
   Number of LUT4s:         66 out of  1280 (5%)
      Number used as logic LUTs:         42
      Number used as distributed RAM:     0
      Number used as ripple logic:       24
      Number used as shift registers:     0
   Number of PIO sites used: 7 + 4(JTAG) out of 80 (14%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net Clock_c: 23 loads, 23 rising, 0 falling (Driver: PIO Clock )
   Number of Clock Enables:  4
     Net VState_1__N_58: 8 loads, 8 LSLICEs
     Net Clock_c_enable_1: 1 loads, 1 LSLICEs

     Net Clock_c_enable_2: 1 loads, 1 LSLICEs
     Net Clock_c_enable_3: 1 loads, 1 LSLICEs
   Number of LSRs:  3
     Net n426: 3 loads, 3 LSLICEs
     Net VState_1__N_58: 6 loads, 6 LSLICEs
     Net n525: 6 loads, 6 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net VState_1__N_58: 20 loads
     Net HCounter_4: 11 loads
     Net VCounter_4: 9 loads
     Net VCounter_1: 7 loads
     Net HCounter_5: 6 loads
     Net n525: 6 loads
     Net VCounter_5: 6 loads
     Net HCounter_6: 5 loads
     Net HCounter_7: 5 loads
     Net HCounter_8: 4 loads




   Number of warnings:  0
   Number of errors:    0
     




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| VSync_o             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| HSync_o             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Green_o             | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Red_o               | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Blue_o              | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Clock               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Reset               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+







Removed logic

Block i848 undriven or does not drive anything - clipped.
Signal GND_net undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal VCounter_196_add_4_1/S0 undriven or does not drive anything - clipped.
Signal VCounter_196_add_4_1/CI undriven or does not drive anything - clipped.
Signal HCounter_195_add_4_1/S0 undriven or does not drive anything - clipped.
Signal HCounter_195_add_4_1/CI undriven or does not drive anything - clipped.
Signal HCounter_195_add_4_11/S1 undriven or does not drive anything - clipped.
Signal HCounter_195_add_4_11/CO undriven or does not drive anything - clipped.
Signal VCounter_196_add_4_11/S1 undriven or does not drive anything - clipped.
Signal VCounter_196_add_4_11/CO undriven or does not drive anything - clipped.
Block i1 was optimized away.

     



GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset
        of the design. The reset signal used for GSR control is 'Reset_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 23 

     Type and instance name of component: 
   Register : HCounter_195__i0
   Register : Red_o_62
   Register : Green_o_63
   Register : Blue_o_64
   Register : VCounter_196__i1
   Register : VCounter_196__i0
   Register : VCounter_196__i6
   Register : VCounter_196__i3
   Register : VCounter_196__i5
   Register : VCounter_196__i4
   Register : VCounter_196__i2
   Register : HCounter_195__i9
   Register : VCounter_196__i7
   Register : HCounter_195__i8

   Register : HCounter_195__i7
   Register : HCounter_195__i6
   Register : HCounter_195__i5
   Register : HCounter_195__i4
   Register : HCounter_195__i3
   Register : HCounter_195__i2
   Register : VCounter_196__i8
   Register : VCounter_196__i9
   Register : HCounter_195__i1



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 39 MB
        










































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