Place & Route TRACE Report
Loading design for application trce from file kurs27_impl1.ncd.
Design name: VGA
NCD version: 3.3
Vendor: LATTICE
Device: LCMXO2-1200HC
Package: TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status: Final Version 1.44.
Performance Hardware Data Status: Final Version 34.4.
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Thu Jul 04 21:07:14 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs27_impl1.twr -gui Kurs27_impl1.ncd Kurs27_impl1.prf
Design file: kurs27_impl1.ncd
Preference file: kurs27_impl1.prf
Device,speed: LCMXO2-1200HC,5
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 635 items scored, 0 timing errors detected.
Report: 129.803MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
635 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 32.296ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in HState_FSM_i0 (to Clock_c +)
Delay: 7.554ns (29.3% logic, 70.7% route), 5 logic levels.
Constraint Details:
7.554ns physical path delay SLICE_9 to SLICE_18 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 32.296ns
Physical Path Details:
Data path SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 3.028 R7C12C.F1 to R4C10B.B1 VState_1__N_58
CTOF_DEL --- 0.452 R4C10B.B1 to R4C10B.F1 SLICE_18
ROUTE 1 0.000 R4C10B.F1 to R4C10B.DI1 n437 (to Clock_c)
--------
7.554 (29.3% logic, 70.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R4C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.401ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i4 (from Clock_c +)
Destination: FF Data in HState_FSM_i0 (to Clock_c +)
Delay: 7.449ns (23.7% logic, 76.3% route), 4 logic levels.
Constraint Details:
7.449ns physical path delay SLICE_8 to SLICE_18 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 32.401ns
Physical Path Details:
Data path SLICE_8 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10C.CLK to R7C10C.Q1 SLICE_8 (from Clock_c)
ROUTE 11 1.443 R7C10C.Q1 to R5C11D.B1 HCounter_4
CTOF_DEL --- 0.452 R5C11D.B1 to R5C11D.F1 SLICE_12
ROUTE 1 1.213 R5C11D.F1 to R7C12C.A1 n1003
CTOF_DEL --- 0.452 R7C12C.A1 to R7C12C.F1 SLICE_26
ROUTE 20 3.028 R7C12C.F1 to R4C10B.B1 VState_1__N_58
CTOF_DEL --- 0.452 R4C10B.B1 to R4C10B.F1 SLICE_18
ROUTE 1 0.000 R4C10B.F1 to R4C10B.DI1 n437 (to Clock_c)
--------
7.449 (23.7% logic, 76.3% route), 4 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R4C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.420ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i2 (from Clock_c +)
Destination: FF Data in HState_FSM_i0 (to Clock_c +)
Delay: 7.430ns (29.8% logic, 70.2% route), 5 logic levels.
Constraint Details:
7.430ns physical path delay SLICE_9 to SLICE_18 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 32.420ns
Physical Path Details:
Data path SLICE_9 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q1 SLICE_9 (from Clock_c)
ROUTE 2 0.911 R7C10B.Q1 to R7C11D.B1 HCounter_2
CTOF_DEL --- 0.452 R7C11D.B1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 3.028 R7C12C.F1 to R4C10B.B1 VState_1__N_58
CTOF_DEL --- 0.452 R4C10B.B1 to R4C10B.F1 SLICE_18
ROUTE 1 0.000 R4C10B.F1 to R4C10B.DI1 n437 (to Clock_c)
--------
7.430 (29.8% logic, 70.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R4C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i2 (to Clock_c +)
FF VCounter_196__i1
Delay: 7.317ns (30.3% logic, 69.7% route), 5 logic levels.
Constraint Details:
7.317ns physical path delay SLICE_9 to SLICE_10 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.435ns
Physical Path Details:
Data path SLICE_9 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.262 R4C11B.F0 to R3C12B.LSR n525 (to Clock_c)
--------
7.317 (30.3% logic, 69.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C12B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i0 (to Clock_c +)
Delay: 7.317ns (30.3% logic, 69.7% route), 5 logic levels.
Constraint Details:
7.317ns physical path delay SLICE_9 to SLICE_11 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.435ns
Physical Path Details:
Data path SLICE_9 to SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.262 R4C11B.F0 to R3C12A.LSR n525 (to Clock_c)
--------
7.317 (30.3% logic, 69.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C12A.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i6 (to Clock_c +)
FF VCounter_196__i5
Delay: 7.317ns (30.3% logic, 69.7% route), 5 logic levels.
Constraint Details:
7.317ns physical path delay SLICE_9 to SLICE_4 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.435ns
Physical Path Details:
Data path SLICE_9 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.262 R4C11B.F0 to R3C12D.LSR n525 (to Clock_c)
--------
7.317 (30.3% logic, 69.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C12D.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.435ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i4 (to Clock_c +)
FF VCounter_196__i3
Delay: 7.317ns (30.3% logic, 69.7% route), 5 logic levels.
Constraint Details:
7.317ns physical path delay SLICE_9 to SLICE_6 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.435ns
Physical Path Details:
Data path SLICE_9 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.262 R4C11B.F0 to R3C12C.LSR n525 (to Clock_c)
--------
7.317 (30.3% logic, 69.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C12C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.461ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i9 (to Clock_c +)
Delay: 7.291ns (30.4% logic, 69.6% route), 5 logic levels.
Constraint Details:
7.291ns physical path delay SLICE_9 to SLICE_0 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.461ns
Physical Path Details:
Data path SLICE_9 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.236 R4C11B.F0 to R3C13B.LSR n525 (to Clock_c)
--------
7.291 (30.4% logic, 69.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C13B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.461ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i1 (from Clock_c +)
Destination: FF Data in VCounter_196__i8 (to Clock_c +)
FF VCounter_196__i7
Delay: 7.291ns (30.4% logic, 69.6% route), 5 logic levels.
Constraint Details:
7.291ns physical path delay SLICE_9 to SLICE_1 meets
40.000ns delay constraint less
0.000ns skew and
0.248ns LSR_SET requirement (totaling 39.752ns) by 32.461ns
Physical Path Details:
Data path SLICE_9 to SLICE_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10B.CLK to R7C10B.Q0 SLICE_9 (from Clock_c)
ROUTE 2 1.035 R7C10B.Q0 to R7C11D.C1 HCounter_1
CTOF_DEL --- 0.452 R7C11D.C1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 1.529 R7C12C.F1 to R4C11B.C0 VState_1__N_58
CTOF_DEL --- 0.452 R4C11B.C0 to R4C11B.F0 SLICE_34
ROUTE 6 1.236 R4C11B.F0 to R3C13A.LSR n525 (to Clock_c)
--------
7.291 (30.4% logic, 69.6% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_9:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R3C13A.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 32.473ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i3 (from Clock_c +)
Destination: FF Data in HState_FSM_i0 (to Clock_c +)
Delay: 7.377ns (30.1% logic, 69.9% route), 5 logic levels.
Constraint Details:
7.377ns physical path delay SLICE_8 to SLICE_18 meets
40.000ns delay constraint less
0.000ns skew and
0.150ns DIN_SET requirement (totaling 39.850ns) by 32.473ns
Physical Path Details:
Data path SLICE_8 to SLICE_18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.409 R7C10C.CLK to R7C10C.Q0 SLICE_8 (from Clock_c)
ROUTE 2 0.858 R7C10C.Q0 to R7C11D.A1 HCounter_3
CTOF_DEL --- 0.452 R7C11D.A1 to R7C11D.F1 SLICE_25
ROUTE 3 0.392 R7C11D.F1 to R7C11D.C0 n881
CTOF_DEL --- 0.452 R7C11D.C0 to R7C11D.F0 SLICE_25
ROUTE 1 0.882 R7C11D.F0 to R7C12C.B1 n1001
CTOF_DEL --- 0.452 R7C12C.B1 to R7C12C.F1 SLICE_26
ROUTE 20 3.028 R7C12C.F1 to R4C10B.B1 VState_1__N_58
CTOF_DEL --- 0.452 R4C10B.B1 to R4C10B.F1 SLICE_18
ROUTE 1 0.000 R4C10B.F1 to R4C10B.DI1 n437 (to Clock_c)
--------
7.377 (30.1% logic, 69.9% route), 5 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_8:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R7C10C.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_18:
Name Fanout Delay (ns) Site Resource
ROUTE 23 2.001 20.PADDI to R4C10B.CLK Clock_c
--------
2.001 (0.0% logic, 100.0% route), 0 logic levels.
Report: 129.803MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | 25.000 MHz| 129.803 MHz| 5
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 23
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 635 paths, 1 nets, and 251 connections (98.05% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2
Thu Jul 04 21:07:14 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs27_impl1.twr -gui Kurs27_impl1.ncd Kurs27_impl1.prf
Design file: kurs27_impl1.ncd
Preference file: kurs27_impl1.prf
Device,speed: LCMXO2-1200HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "Clock" 25.000000 MHz (0 errors) 635 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "Clock" 25.000000 MHz ;
635 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i9 (from Clock_c +)
Destination: FF Data in VCounter_196__i9 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_0 to SLICE_0 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_0 to SLICE_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C13B.CLK to R3C13B.Q0 SLICE_0 (from Clock_c)
ROUTE 3 0.132 R3C13B.Q0 to R3C13B.A0 VCounter_9
CTOF_DEL --- 0.101 R3C13B.A0 to R3C13B.F0 SLICE_0
ROUTE 1 0.000 R3C13B.F0 to R3C13B.DI0 n36 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C13B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C13B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i2 (from Clock_c +)
Destination: FF Data in VCounter_196__i2 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_10 to SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_10 to SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12B.CLK to R3C12B.Q1 SLICE_10 (from Clock_c)
ROUTE 3 0.132 R3C12B.Q1 to R3C12B.A1 VCounter_2
CTOF_DEL --- 0.101 R3C12B.A1 to R3C12B.F1 SLICE_10
ROUTE 1 0.000 R3C12B.F1 to R3C12B.DI1 n43 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12B.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i0 (from Clock_c +)
Destination: FF Data in VCounter_196__i0 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_11 to SLICE_11 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_11 to SLICE_11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12A.CLK to R3C12A.Q1 SLICE_11 (from Clock_c)
ROUTE 3 0.132 R3C12A.Q1 to R3C12A.A1 VCounter_0
CTOF_DEL --- 0.101 R3C12A.A1 to R3C12A.F1 SLICE_11
ROUTE 1 0.000 R3C12A.F1 to R3C12A.DI1 n45 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_11:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VState_FSM_i0_i0 (from Clock_c +)
Destination: FF Data in VState_FSM_i0_i0 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_22 to SLICE_22 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_22 to SLICE_22:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C11C.CLK to R4C11C.Q0 SLICE_22 (from Clock_c)
ROUTE 2 0.132 R4C11C.Q0 to R4C11C.A0 n280
CTOF_DEL --- 0.101 R4C11C.A0 to R4C11C.F0 SLICE_22
ROUTE 1 0.000 R4C11C.F0 to R4C11C.DI0 n448 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R4C11C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_22:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R4C11C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i7 (from Clock_c +)
Destination: FF Data in HCounter_195__i7 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_3 to SLICE_3 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_3 to SLICE_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C11A.CLK to R7C11A.Q0 SLICE_3 (from Clock_c)
ROUTE 5 0.132 R7C11A.Q0 to R7C11A.A0 HCounter_7
CTOF_DEL --- 0.101 R7C11A.A0 to R7C11A.F0 SLICE_3
ROUTE 1 0.000 R7C11A.F0 to R7C11A.DI0 n48 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R7C11A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_3:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R7C11A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i6 (from Clock_c +)
Destination: FF Data in VCounter_196__i6 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_4 to SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12D.CLK to R3C12D.Q1 SLICE_4 (from Clock_c)
ROUTE 4 0.132 R3C12D.Q1 to R3C12D.A1 VCounter_6
CTOF_DEL --- 0.101 R3C12D.A1 to R3C12D.F1 SLICE_4
ROUTE 1 0.000 R3C12D.F1 to R3C12D.DI1 n39 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i5 (from Clock_c +)
Destination: FF Data in VCounter_196__i5 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_4 to SLICE_4 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_4 to SLICE_4:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12D.CLK to R3C12D.Q0 SLICE_4 (from Clock_c)
ROUTE 6 0.132 R3C12D.Q0 to R3C12D.A0 VCounter_5
CTOF_DEL --- 0.101 R3C12D.A0 to R3C12D.F0 SLICE_4
ROUTE 1 0.000 R3C12D.F0 to R3C12D.DI0 n40 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_4:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12D.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q HCounter_195__i0 (from Clock_c +)
Destination: FF Data in HCounter_195__i0 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_5 to SLICE_5 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_5 to SLICE_5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R7C10A.CLK to R7C10A.Q1 SLICE_5 (from Clock_c)
ROUTE 2 0.132 R7C10A.Q1 to R7C10A.A1 HCounter_0
CTOF_DEL --- 0.101 R7C10A.A1 to R7C10A.F1 SLICE_5
ROUTE 1 0.000 R7C10A.F1 to R7C10A.DI1 n55 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R7C10A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_5:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R7C10A.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i3 (from Clock_c +)
Destination: FF Data in VCounter_196__i3 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_6 to SLICE_6 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_6 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12C.CLK to R3C12C.Q0 SLICE_6 (from Clock_c)
ROUTE 3 0.132 R3C12C.Q0 to R3C12C.A0 VCounter_3
CTOF_DEL --- 0.101 R3C12C.A0 to R3C12C.F0 SLICE_6
ROUTE 1 0.000 R3C12C.F0 to R3C12C.DI0 n42 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q VCounter_196__i4 (from Clock_c +)
Destination: FF Data in VCounter_196__i4 (to Clock_c +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay SLICE_6 to SLICE_6 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path SLICE_6 to SLICE_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C12C.CLK to R3C12C.Q1 SLICE_6 (from Clock_c)
ROUTE 9 0.132 R3C12C.Q1 to R3C12C.A1 VCounter_4
CTOF_DEL --- 0.101 R3C12C.A1 to R3C12C.F1 SLICE_6
ROUTE 1 0.000 R3C12C.F1 to R3C12C.DI1 n41 (to Clock_c)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path Clock to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path Clock to SLICE_6:
Name Fanout Delay (ns) Site Resource
ROUTE 23 0.773 20.PADDI to R3C12C.CLK Clock_c
--------
0.773 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "Clock" 25.000000 MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 1 clocks:
Clock Domain: Clock_c Source: Clock.PAD Loads: 23
Covered under: FREQUENCY PORT "Clock" 25.000000 MHz ;
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 635 paths, 1 nets, and 251 connections (98.05% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
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