Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sun Jul 21 12:03:02 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     VGA
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
            803 items scored, 561 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 3.218ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             HCounter_195__i1  (from Clock_c +)
   Destination:    FD1P3IX    CD             VCounter_196__i9  (to Clock_c +)

   Delay:                   8.072ns  (27.2% logic, 72.8% route), 5 logic levels.

 Constraint Details:

      8.072ns data_path HCounter_195__i1 to VCounter_196__i9 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 3.218ns

 Path Details: HCounter_195__i1 to VCounter_196__i9

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              HCounter_195__i1 (from Clock_c)
Route         2   e 1.002                                  HCounter[1]
LUT4        ---     0.448              D to Z              i3_4_lut_adj_4
Route         3   e 1.051                                  n881
LUT4        ---     0.448              B to Z              i2_3_lut_rep_7
Route         1   e 0.788                                  n1001
LUT4        ---     0.448              C to Z              i847_4_lut
Route        28   e 1.696                                  VState_1__N_58
LUT4        ---     0.448              B to Z              i839_2_lut_2_lut
Route        10   e 1.340                                  n525
                  --------
                    8.072  (27.2% logic, 72.8% route), 5 logic levels.


Error:  The following path violates requirements by 3.218ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             HCounter_195__i1  (from Clock_c +)
   Destination:    FD1P3IX    CD             VCounter_196__i8  (to Clock_c +)

   Delay:                   8.072ns  (27.2% logic, 72.8% route), 5 logic levels.

 Constraint Details:

      8.072ns data_path HCounter_195__i1 to VCounter_196__i8 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 3.218ns

 Path Details: HCounter_195__i1 to VCounter_196__i8

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              HCounter_195__i1 (from Clock_c)
Route         2   e 1.002                                  HCounter[1]
LUT4        ---     0.448              D to Z              i3_4_lut_adj_4
Route         3   e 1.051                                  n881
LUT4        ---     0.448              B to Z              i2_3_lut_rep_7
Route         1   e 0.788                                  n1001
LUT4        ---     0.448              C to Z              i847_4_lut
Route        28   e 1.696                                  VState_1__N_58
LUT4        ---     0.448              B to Z              i839_2_lut_2_lut
Route        10   e 1.340                                  n525
                  --------
                    8.072  (27.2% logic, 72.8% route), 5 logic levels.


Error:  The following path violates requirements by 3.218ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1S3IX    CK             HCounter_195__i1  (from Clock_c +)
   Destination:    FD1P3IX    CD             VCounter_196__i7  (to Clock_c +)

   Delay:                   8.072ns  (27.2% logic, 72.8% route), 5 logic levels.

 Constraint Details:

      8.072ns data_path HCounter_195__i1 to VCounter_196__i7 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 3.218ns

 Path Details: HCounter_195__i1 to VCounter_196__i7

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              HCounter_195__i1 (from Clock_c)
Route         2   e 1.002                                  HCounter[1]
LUT4        ---     0.448              D to Z              i3_4_lut_adj_4
Route         3   e 1.051                                  n881
LUT4        ---     0.448              B to Z              i2_3_lut_rep_7
Route         1   e 0.788                                  n1001
LUT4        ---     0.448              C to Z              i847_4_lut
Route        28   e 1.696                                  VState_1__N_58
LUT4        ---     0.448              B to Z              i839_2_lut_2_lut
Route        10   e 1.340                                  n525
                  --------
                    8.072  (27.2% logic, 72.8% route), 5 logic levels.

Warning: 8.218 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock_c]                 |     5.000 ns|     8.218 ns|     5 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
VState_1__N_58                          |      28|     326|     58.11%
                                        |        |        |
n1001                                   |       1|     222|     39.57%
                                        |        |        |
n525                                    |      10|     200|     35.65%
                                        |        |        |
n881                                    |       3|     172|     30.66%
                                        |        |        |
n1000                                   |       3|     120|     21.39%
                                        |        |        |
n1003                                   |       1|      74|     13.19%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 561  Score: 739625

Constraints cover  803 paths, 101 nets, and 272 connections (97.8% coverage)


Peak memory: 56160256 bytes, TRCE: 2105344 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs