Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.13.0.56.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Sun Jul 21 12:03:02 2024 Command Line: synthesis -f Kurs27_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs27/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = VGA. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Lattice/Kurs27 (searchpath added) -p C:/lscc/diamond/3.13/ispfpga/xo2c00/data (searchpath added) -p C:/Lattice/Kurs27/impl1 (searchpath added) -p C:/Lattice/Kurs27 (searchpath added) Verilog design file = C:/Lattice/Kurs27/impl1/source/vga.v NGD file = Kurs27_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/lattice/kurs27/impl1/source/vga.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): VGA INFO - synthesis: c:/lattice/kurs27/impl1/source/vga.v(4): compiling module VGA. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga. Package Status: Final Version 1.44. Top-level module name = VGA. INFO - synthesis: Extracted state machine for register 'HState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 INFO - synthesis: Extracted state machine for register 'VState' with one-hot encoding original encoding -> new encoding (one-hot encoding) 00 -> 0001 01 -> 0010 10 -> 0100 11 -> 1000 GSR instance connected to net Reset_c. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in VGA_drc.log. Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs27_impl1.ngd. ################### Begin Area Report (VGA)###################### Number of register bits => 33 of 1520 (2 % ) CCU2D => 12 FD1P3AX => 3 FD1P3AY => 2 FD1P3IX => 10 FD1S3AX => 3 FD1S3AY => 2 FD1S3IX => 13 GSR => 1 IB => 2 LUT4 => 42 OB => 5 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock_c, loads : 33 Clock Enable Nets Number of Clock Enables: 4 Top 4 highest fanout Clock Enables: Net : VState_1__N_58, loads : 28 Net : Clock_c_enable_1, loads : 1 Net : Clock_c_enable_2, loads : 1 Net : Clock_c_enable_3, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : VState_1__N_58, loads : 28 Net : HCounter_4, loads : 11 Net : n525, loads : 10 Net : VCounter_4, loads : 9 Net : VCounter_1, loads : 7 Net : HCounter_5, loads : 6 Net : VCounter_5, loads : 6 Net : HCounter_7, loads : 5 Net : HCounter_6, loads : 5 Net : HCounter_9, loads : 4 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock_c] | 200.000 MHz| 121.684 MHz| 5 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 53.707 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.094 secs --------------------------------------------------------------