# TCL File Generated by Component Editor 16.0
# Tue Jun 27 19:33:15 CEST 2017
# DO NOT MODIFY


# 
# hex7led "hex7led" v1.0
#  2017.06.27.19:33:15
# 
# 

# 
# request TCL package from ACDS 16.0
# 
package require -exact qsys 16.0


# 
# module hex7led
# 
set_module_property DESCRIPTION ""
set_module_property NAME hex7led
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME hex7led
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false


# 
# file sets
# 
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL x7seg
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file counter_n_bit.vhd VHDL PATH ../7seg_AVALON/counter_n_bit.vhd
add_fileset_file demux4n1.vhd VHDL PATH ../7seg_AVALON/demux4n1.vhd
add_fileset_file hex7seg.vhd VHDL PATH ../7seg_AVALON/hex7seg.vhd
add_fileset_file mux16n4.vhd VHDL PATH ../7seg_AVALON/mux16n4.vhd
add_fileset_file x7seg.vhd VHDL PATH ../7seg_AVALON/x7seg.vhd TOP_LEVEL_FILE

add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL x7seg
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file counter_n_bit.vhd VHDL PATH ../7seg_AVALON/counter_n_bit.vhd
add_fileset_file demux4n1.vhd VHDL PATH ../7seg_AVALON/demux4n1.vhd
add_fileset_file hex7seg.vhd VHDL PATH ../7seg_AVALON/hex7seg.vhd
add_fileset_file mux16n4.vhd VHDL PATH ../7seg_AVALON/mux16n4.vhd
add_fileset_file x7seg.vhd VHDL PATH ../7seg_AVALON/x7seg.vhd

add_fileset SIM_VHDL SIM_VHDL "" ""
set_fileset_property SIM_VHDL TOP_LEVEL x7seg
set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file counter_n_bit.vhd VHDL PATH ../7seg_AVALON/counter_n_bit.vhd
add_fileset_file demux4n1.vhd VHDL PATH ../7seg_AVALON/demux4n1.vhd
add_fileset_file hex7seg.vhd VHDL PATH ../7seg_AVALON/hex7seg.vhd
add_fileset_file mux16n4.vhd VHDL PATH ../7seg_AVALON/mux16n4.vhd
add_fileset_file x7seg.vhd VHDL PATH ../7seg_AVALON/x7seg.vhd


# 
# parameters
# 


# 
# display items
# 


# 
# connection point avalon_slave_0
# 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
set_interface_property avalon_slave_0 EXPORT_OF ""
set_interface_property avalon_slave_0 PORT_NAME_MAP ""
set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""

add_interface_port avalon_slave_0 x writedata Input 16
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 chipselect chipselect Input 1
add_interface_port avalon_slave_0 byteenable byteenable Input 2
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0


# 
# connection point clock
# 
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""

add_interface_port clock clk clk Input 1


# 
# connection point reset
# 
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""

add_interface_port reset resetn reset_n Input 1


# 
# connection point segment
# 
add_interface segment conduit end
set_interface_property segment associatedClock clock
set_interface_property segment associatedReset ""
set_interface_property segment ENABLED true
set_interface_property segment EXPORT_OF ""
set_interface_property segment PORT_NAME_MAP ""
set_interface_property segment CMSIS_SVD_VARIABLES ""
set_interface_property segment SVD_ADDRESS_GROUP ""

add_interface_port segment seg new_signal Output 8


# 
# connection point digit
# 
add_interface digit conduit end
set_interface_property digit associatedClock clock
set_interface_property digit associatedReset ""
set_interface_property digit ENABLED true
set_interface_property digit EXPORT_OF ""
set_interface_property digit PORT_NAME_MAP ""
set_interface_property digit CMSIS_SVD_VARIABLES ""
set_interface_property digit SVD_ADDRESS_GROUP ""

add_interface_port digit dig new_signal Output 4

