	component NIOS_LED is
		port (
			clk_clk                      : in  std_logic                    := 'X'; -- clk
			led_export                   : out std_logic_vector(3 downto 0);        -- export
			hex7led_0_segment_new_signal : out std_logic_vector(7 downto 0);        -- new_signal
			hex7led_0_digit_new_signal   : out std_logic_vector(3 downto 0)         -- new_signal
		);
	end component NIOS_LED;

	u0 : component NIOS_LED
		port map (
			clk_clk                      => CONNECTED_TO_clk_clk,                      --               clk.clk
			led_export                   => CONNECTED_TO_led_export,                   --               led.export
			hex7led_0_segment_new_signal => CONNECTED_TO_hex7led_0_segment_new_signal, -- hex7led_0_segment.new_signal
			hex7led_0_digit_new_signal   => CONNECTED_TO_hex7led_0_digit_new_signal    --   hex7led_0_digit.new_signal
		);

