# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, the Altera Quartus Prime License Agreement,
# the Altera MegaCore Function License Agreement, or other 
# applicable license agreement, including, without limitation, 
# that your use is for the sole purpose of programming logic 
# devices manufactured by Altera and sold by Altera or its 
# authorized distributors.  Please refer to the applicable 
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition
# Date created = 20:04:16  September 22, 2016
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		NIOS_LED_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08DAF256C8GES
set_global_assignment -name TOP_LEVEL_ENTITY NIOS_LED
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:04:16  SEPTEMBER 22, 2016"
set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_L3 -to clk_clk
set_location_assignment PIN_R16 -to led_export[3]
set_location_assignment PIN_P16 -to led_export[2]
set_location_assignment PIN_N16 -to led_export[1]
set_location_assignment PIN_M16 -to led_export[0]


set_global_assignment -name QIP_FILE software/NIOS_LED/mem_init/meminit.qip
set_global_assignment -name QIP_FILE NIOS_LED/synthesis/NIOS_LED.qip
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name PROJECT_IP_REGENERATION_POLICY ALWAYS_REGENERATE_IP
set_location_assignment PIN_H2 -to altera_reserved_tms
set_location_assignment PIN_H3 -to altera_reserved_tck
set_location_assignment PIN_G1 -to altera_reserved_tdi
set_location_assignment PIN_H1 -to altera_reserved_tdo
set_location_assignment PIN_F8 -to ~ALTERA_CONFIG_SEL~
set_location_assignment PIN_E8 -to ~ALTERA_nCONFIG~
set_location_assignment PIN_F7 -to ~ALTERA_nSTATUS~
set_location_assignment PIN_E7 -to ~ALTERA_CONF_DONE~
set_location_assignment PIN_L16 -to hex7led_0_segment_new_signal[0]
set_location_assignment PIN_J15 -to hex7led_0_segment_new_signal[1]
set_location_assignment PIN_J16 -to hex7led_0_segment_new_signal[2]
set_location_assignment PIN_H15 -to hex7led_0_segment_new_signal[3]
set_location_assignment PIN_H16 -to hex7led_0_segment_new_signal[4]
set_location_assignment PIN_G15 -to hex7led_0_segment_new_signal[5]
set_location_assignment PIN_G16 -to hex7led_0_segment_new_signal[6]
set_location_assignment PIN_F16 -to hex7led_0_segment_new_signal[7]
set_location_assignment PIN_E15 -to hex7led_0_digit_new_signal[0]
set_location_assignment PIN_E16 -to hex7led_0_digit_new_signal[1]
set_location_assignment PIN_D15 -to hex7led_0_digit_new_signal[2]
set_location_assignment PIN_D16 -to hex7led_0_digit_new_signal[3]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top