{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1498584933235 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498584933235 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 19:35:33 2017 " "Processing started: Tue Jun 27 19:35:33 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498584933235 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584933235 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off NIOS_LED -c NIOS_LED " "Command: quartus_map --read_settings_files=on --write_settings_files=off NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584933235 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1498584934079 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1498584934079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/nios_led.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/nios_led.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NIOS_LED-rtl " "Found design unit 1: NIOS_LED-rtl" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 18 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946001 ""} { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED " "Found entity 1: NIOS_LED" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946001 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946001 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_reset_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_reset_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_controller " "Found entity 1: altera_reset_controller" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 42 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946017 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_reset_synchronizer.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_reset_synchronizer.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_reset_synchronizer " "Found entity 1: altera_reset_synchronizer" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_synchronizer.v" 24 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946017 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_irq_mapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_irq_mapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_irq_mapper " "Found entity 1: NIOS_LED_irq_mapper" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_irq_mapper.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_irq_mapper.sv" 31 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946017 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0 " "Found entity 1: NIOS_LED_mm_interconnect_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946017 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_001.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_001.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_avalon_st_adapter_001 " "Found entity 1: NIOS_LED_mm_interconnect_0_avalon_st_adapter_001" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946017 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946017 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 " "Found entity 1: NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_avalon_st_adapter " "Found entity 1: NIOS_LED_mm_interconnect_0_avalon_st_adapter" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_width_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_width_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_width_adapter " "Found entity 1: altera_merlin_width_adapter" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_address_alignment.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_address_alignment.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_address_alignment " "Found entity 1: altera_merlin_address_alignment" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_address_alignment.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_address_alignment.sv" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_uncompressor.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_uncompressor.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946032 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946032 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_rsp_mux_001 " "Found entity 1: NIOS_LED_mm_interconnect_0_rsp_mux_001" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux_001.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" 103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" 228 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_rsp_mux " "Found entity 1: NIOS_LED_mm_interconnect_0_rsp_mux" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_rsp_demux " "Found entity 1: NIOS_LED_mm_interconnect_0_rsp_demux" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_demux.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_mux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_mux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_cmd_mux_001 " "Found entity 1: NIOS_LED_mm_interconnect_0_cmd_mux_001" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux_001.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_cmd_mux " "Found entity 1: NIOS_LED_mm_interconnect_0_cmd_mux" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_demux_001.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_demux_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_cmd_demux_001 " "Found entity 1: NIOS_LED_mm_interconnect_0_cmd_demux_001" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_demux_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_demux_001.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_cmd_demux " "Found entity 1: NIOS_LED_mm_interconnect_0_cmd_demux" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_demux.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946048 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946048 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_burst_adapter.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_burst_adapter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter " "Found entity 1: altera_merlin_burst_adapter" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter.sv" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_uncompressed_only " "Found entity 1: altera_merlin_burst_adapter_uncompressed_only" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_uncmpr.sv" 39 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv 5 5 " "Found 5 design units, including 5 entities, in source file nios_led/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_burstwrap_increment " "Found entity 1: altera_merlin_burst_adapter_burstwrap_increment" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_burst_adapter_adder " "Found entity 2: altera_merlin_burst_adapter_adder" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 55 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""} { "Info" "ISGN_ENTITY_NAME" "3 altera_merlin_burst_adapter_subtractor " "Found entity 3: altera_merlin_burst_adapter_subtractor" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 77 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""} { "Info" "ISGN_ENTITY_NAME" "4 altera_merlin_burst_adapter_min " "Found entity 4: altera_merlin_burst_adapter_min" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 98 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""} { "Info" "ISGN_ENTITY_NAME" "5 altera_merlin_burst_adapter_13_1 " "Found entity 5: altera_merlin_burst_adapter_13_1" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_13_1.sv" 264 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BYTE_TO_WORD_SHIFT byte_to_word_shift altera_merlin_burst_adapter_new.sv(139) " "Verilog HDL Declaration information at altera_merlin_burst_adapter_new.sv(139): object \"BYTE_TO_WORD_SHIFT\" differs only in case from object \"byte_to_word_shift\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 139 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_burst_adapter_new.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_burst_adapter_new.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_adapter_new " "Found entity 1: altera_merlin_burst_adapter_new" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_new.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter_new.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_incr_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_incr_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_incr_burst_converter " "Found entity 1: altera_incr_burst_converter" {  } { { "NIOS_LED/synthesis/submodules/altera_incr_burst_converter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_incr_burst_converter.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946063 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946063 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "addr_incr ADDR_INCR altera_wrap_burst_converter.sv(279) " "Verilog HDL Declaration information at altera_wrap_burst_converter.sv(279): object \"addr_incr\" differs only in case from object \"ADDR_INCR\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_wrap_burst_converter.sv" 279 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_wrap_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_wrap_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_wrap_burst_converter " "Found entity 1: altera_wrap_burst_converter" {  } { { "NIOS_LED/synthesis/submodules/altera_wrap_burst_converter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_wrap_burst_converter.sv" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_default_burst_converter.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_default_burst_converter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_default_burst_converter " "Found entity 1: altera_default_burst_converter" {  } { { "NIOS_LED/synthesis/submodules/altera_default_burst_converter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_default_burst_converter.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_avalon_st_pipeline_stage.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_stage " "Found entity 1: altera_avalon_st_pipeline_stage" {  } { { "NIOS_LED/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_avalon_st_pipeline_stage.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_avalon_st_pipeline_base.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_avalon_st_pipeline_base.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_st_pipeline_base " "Found entity 1: altera_avalon_st_pipeline_base" {  } { { "NIOS_LED/synthesis/submodules/altera_avalon_st_pipeline_base.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_avalon_st_pipeline_base.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel NIOS_LED_mm_interconnect_0_router_005.sv(48) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_005.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel NIOS_LED_mm_interconnect_0_router_005.sv(49) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_005.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_005.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_005.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_router_005_default_decode " "Found entity 1: NIOS_LED_mm_interconnect_0_router_005_default_decode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_mm_interconnect_0_router_005 " "Found entity 2: NIOS_LED_mm_interconnect_0_router_005" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel NIOS_LED_mm_interconnect_0_router_003.sv(48) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_003.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel NIOS_LED_mm_interconnect_0_router_003.sv(49) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_003.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_003.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_003.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_router_003_default_decode " "Found entity 1: NIOS_LED_mm_interconnect_0_router_003_default_decode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_mm_interconnect_0_router_003 " "Found entity 2: NIOS_LED_mm_interconnect_0_router_003" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel NIOS_LED_mm_interconnect_0_router_002.sv(48) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_002.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel NIOS_LED_mm_interconnect_0_router_002.sv(49) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_002.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_002.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_002.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_router_002_default_decode " "Found entity 1: NIOS_LED_mm_interconnect_0_router_002_default_decode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_mm_interconnect_0_router_002 " "Found entity 2: NIOS_LED_mm_interconnect_0_router_002" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946079 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946079 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel NIOS_LED_mm_interconnect_0_router_001.sv(48) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel NIOS_LED_mm_interconnect_0_router_001.sv(49) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_router_001_default_decode " "Found entity 1: NIOS_LED_mm_interconnect_0_router_001_default_decode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_mm_interconnect_0_router_001 " "Found entity 2: NIOS_LED_mm_interconnect_0_router_001" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel NIOS_LED_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel NIOS_LED_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at NIOS_LED_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file nios_led/synthesis/submodules/nios_led_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_mm_interconnect_0_router_default_decode " "Found entity 1: NIOS_LED_mm_interconnect_0_router_default_decode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_mm_interconnect_0_router " "Found entity 2: NIOS_LED_mm_interconnect_0_router" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" {  } { { "NIOS_LED/synthesis/submodules/altera_avalon_sc_fifo.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_avalon_sc_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_master_agent.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946095 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946095 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_slave_translator.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_slave_translator.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_master_translator.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_master_translator.sv" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_timer_0.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_timer_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_timer_0 " "Found entity 1: NIOS_LED_timer_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_timer_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_timer_0.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_pio_0.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_pio_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_pio_0 " "Found entity 1: NIOS_LED_pio_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_pio_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_pio_0.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_onchip_memory2_0.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_onchip_memory2_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_onchip_memory2_0 " "Found entity 1: NIOS_LED_onchip_memory2_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0 " "Found entity 1: NIOS_LED_nios2_gen2_0" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946110 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946110 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu.v 21 21 " "Found 21 design units, including 21 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module " "Found entity 1: NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "2 NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module " "Found entity 2: NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 86 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "3 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug " "Found entity 3: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 151 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "4 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break " "Found entity 4: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 292 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "5 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk " "Found entity 5: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 584 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "6 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk " "Found entity 6: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 790 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "7 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace " "Found entity 7: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 976 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "8 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode " "Found entity 8: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1110 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "9 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace " "Found entity 9: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1177 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "10 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt " "Found entity 10: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1258 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "11 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc " "Found entity 11: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1329 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "12 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc " "Found entity 12: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1371 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "13 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo " "Found entity 13: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1417 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "14 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib " "Found entity 14: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1902 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "15 NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im " "Found entity 15: NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1924 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "16 NIOS_LED_nios2_gen2_0_cpu_nios2_performance_monitors " "Found entity 16: NIOS_LED_nios2_gen2_0_cpu_nios2_performance_monitors" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1993 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "17 NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg " "Found entity 17: NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2009 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "18 NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module " "Found entity 18: NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "19 NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem " "Found entity 19: NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2165 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "20 NIOS_LED_nios2_gen2_0_cpu_nios2_oci " "Found entity 20: NIOS_LED_nios2_gen2_0_cpu_nios2_oci" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2345 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""} { "Info" "ISGN_ENTITY_NAME" "21 NIOS_LED_nios2_gen2_0_cpu " "Found entity 21: NIOS_LED_nios2_gen2_0_cpu" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2820 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946126 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946126 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_sysclk.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_sysclk.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk " "Found entity 1: NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_tck.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_tck.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck " "Found entity 1: NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_debug_slave_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper " "Found entity 1: NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_test_bench.v 1 1 " "Found 1 design units, including 1 entities, in source file nios_led/synthesis/submodules/nios_led_nios2_gen2_0_cpu_test_bench.v" { { "Info" "ISGN_ENTITY_NAME" "1 NIOS_LED_nios2_gen2_0_cpu_test_bench " "Found entity 1: NIOS_LED_nios2_gen2_0_cpu_test_bench" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_test_bench.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_test_bench.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/counter_n_bit.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/submodules/counter_n_bit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter_n_bit-logic " "Found design unit 1: counter_n_bit-logic" {  } { { "NIOS_LED/synthesis/submodules/counter_n_bit.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/counter_n_bit.vhd" 18 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""} { "Info" "ISGN_ENTITY_NAME" "1 counter_n_bit " "Found entity 1: counter_n_bit" {  } { { "NIOS_LED/synthesis/submodules/counter_n_bit.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/counter_n_bit.vhd" 12 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/demux4n1.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/submodules/demux4n1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 demux4n1-logic " "Found design unit 1: demux4n1-logic" {  } { { "NIOS_LED/synthesis/submodules/demux4n1.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/demux4n1.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""} { "Info" "ISGN_ENTITY_NAME" "1 demux4n1 " "Found entity 1: demux4n1" {  } { { "NIOS_LED/synthesis/submodules/demux4n1.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/demux4n1.vhd" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/hex7seg.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/submodules/hex7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 hex7seg-logic " "Found design unit 1: hex7seg-logic" {  } { { "NIOS_LED/synthesis/submodules/hex7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/hex7seg.vhd" 14 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""} { "Info" "ISGN_ENTITY_NAME" "1 hex7seg " "Found entity 1: hex7seg" {  } { { "NIOS_LED/synthesis/submodules/hex7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/hex7seg.vhd" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946142 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/mux16n4.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/submodules/mux16n4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 mux16n4-logic " "Found design unit 1: mux16n4-logic" {  } { { "NIOS_LED/synthesis/submodules/mux16n4.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/mux16n4.vhd" 15 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946157 ""} { "Info" "ISGN_ENTITY_NAME" "1 mux16n4 " "Found entity 1: mux16n4" {  } { { "NIOS_LED/synthesis/submodules/mux16n4.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/mux16n4.vhd" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946157 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946157 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "nios_led/synthesis/submodules/x7seg.vhd 2 1 " "Found 2 design units, including 1 entities, in source file nios_led/synthesis/submodules/x7seg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 x7seg-logic " "Found design unit 1: x7seg-logic" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 22 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946157 ""} { "Info" "ISGN_ENTITY_NAME" "1 x7seg " "Found entity 1: x7seg" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 10 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946157 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946157 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "NIOS_LED " "Elaborating entity \"NIOS_LED\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1498584946313 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "x7seg x7seg:hex7led_0 " "Elaborating entity \"x7seg\" for hierarchy \"x7seg:hex7led_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "hex7led_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 279 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 ""}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "be x7seg.vhd(63) " "VHDL Process Statement warning at x7seg.vhd(63): signal \"be\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "x x7seg.vhd(63) " "VHDL Process Statement warning at x7seg.vhd(63): signal \"x\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 63 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "be x7seg.vhd(64) " "VHDL Process Statement warning at x7seg.vhd(64): signal \"be\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "x x7seg.vhd(64) " "VHDL Process Statement warning at x7seg.vhd(64): signal \"x\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 64 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "x_sig x7seg.vhd(55) " "VHDL Process Statement warning at x7seg.vhd(55): inferring latch(es) for signal or variable \"x_sig\", which holds its previous value in one or more paths through the process" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[0\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[0\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[1\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[1\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[2\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[2\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[3\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[3\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[4\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[4\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[5\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[5\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[6\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[6\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[7\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[7\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[8\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[8\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[9\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[9\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[10\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[10\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[11\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[11\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[12\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[12\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[13\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[13\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[14\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[14\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "x_sig\[15\] x7seg.vhd(55) " "Inferred latch for \"x_sig\[15\]\" at x7seg.vhd(55)" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 "|NIOS_LED|x7seg:hex7led_0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mux16n4 x7seg:hex7led_0\|mux16n4:U1 " "Elaborating entity \"mux16n4\" for hierarchy \"x7seg:hex7led_0\|mux16n4:U1\"" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "U1" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 69 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "hex7seg x7seg:hex7led_0\|hex7seg:U2 " "Elaborating entity \"hex7seg\" for hierarchy \"x7seg:hex7led_0\|hex7seg:U2\"" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "U2" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 70 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "demux4n1 x7seg:hex7led_0\|demux4n1:U3 " "Elaborating entity \"demux4n1\" for hierarchy \"x7seg:hex7led_0\|demux4n1:U3\"" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "U3" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 71 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946360 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter_n_bit x7seg:hex7led_0\|counter_n_bit:U4 " "Elaborating entity \"counter_n_bit\" for hierarchy \"x7seg:hex7led_0\|counter_n_bit:U4\"" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "U4" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 72 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946376 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0 NIOS_LED_nios2_gen2_0:nios2_gen2_0 " "Elaborating entity \"NIOS_LED_nios2_gen2_0\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "nios2_gen2_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 291 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946376 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0.v" "cpu" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0.v" 65 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946376 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_test_bench NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_test_bench:the_NIOS_LED_nios2_gen2_0_cpu_test_bench " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_test_bench\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_test_bench:the_NIOS_LED_nios2_gen2_0_cpu_test_bench\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_test_bench" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 3534 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946392 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "NIOS_LED_nios2_gen2_0_cpu_register_bank_a" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 4050 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946392 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_altsyncram" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 57 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946438 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 57 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946438 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram " "Instantiated megafunction \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "rdcontrol_reg_b CLOCK0 " "Parameter \"rdcontrol_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946438 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 57 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1498584946438 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_s0c1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_s0c1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_s0c1 " "Found entity 1: altsyncram_s0c1" {  } { { "db/altsyncram_s0c1.tdf" "" { Text "C:/ALTERA/NIOS_LED/db/altsyncram_s0c1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946501 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_s0c1 NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_s0c1:auto_generated " "Elaborating entity \"altsyncram_s0c1\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_a_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_a\|altsyncram:the_altsyncram\|altsyncram_s0c1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_b " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_register_bank_b_module:NIOS_LED_nios2_gen2_0_cpu_register_bank_b\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "NIOS_LED_nios2_gen2_0_cpu_register_bank_b" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 4068 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946517 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 4564 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946532 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2516 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946532 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_std_synchronizer NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborating entity \"altera_std_synchronizer\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_altera_std_synchronizer" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 217 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946548 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Elaborated megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 217 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946548 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer " "Instantiated megafunction \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "depth 2 " "Parameter \"depth\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946548 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 217 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1498584946548 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_break" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2546 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946548 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_xbrk" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2567 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dbrk" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2593 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_itrace" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2610 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2625 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode:NIOS_LED_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_dtrace\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_td_mode:NIOS_LED_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1226 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2640 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1535 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1544 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 1553 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_pib" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2645 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_im" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2659 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg:the_NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg:the_NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_avalon_reg" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2678 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2698 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2315 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_altsyncram" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2140 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946610 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2140 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946610 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram " "Instantiated megafunction \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file UNUSED " "Parameter \"init_file\" = \"UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 0 " "Parameter \"maximum_depth\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 256 " "Parameter \"numwords_a\" = \"256\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a DONT_CARE " "Parameter \"read_during_write_mode_port_a\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 8 " "Parameter \"widthad_a\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946610 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2140 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1498584946610 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0n61.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0n61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0n61 " "Found entity 1: altsyncram_0n61" {  } { { "db/altsyncram_0n61.tdf" "" { Text "C:/ALTERA/NIOS_LED/db/altsyncram_0n61.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584946673 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584946673 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0n61 NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_0n61:auto_generated " "Elaborating entity \"altsyncram_0n61\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem:the_NIOS_LED_nios2_gen2_0_cpu_nios2_ocimem\|NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram_module:NIOS_LED_nios2_gen2_0_cpu_ociram_sp_ram\|altsyncram:the_altsyncram\|altsyncram_0n61:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946673 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2800 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946673 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_tck" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 156 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk " "Elaborating entity \"NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_sysclk" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 176 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_basic NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy " "Elaborating entity \"sld_virtual_jtag_basic\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 206 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946720 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy " "Elaborated megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 206 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946720 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy " "Instantiated megafunction \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_auto_instance_index YES " "Parameter \"sld_auto_instance_index\" = \"YES\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_instance_index 0 " "Parameter \"sld_instance_index\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_ir_width 2 " "Parameter \"sld_ir_width\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_mfg_id 70 " "Parameter \"sld_mfg_id\" = \"70\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_action  " "Parameter \"sld_sim_action\" = \"\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_n_scan 0 " "Parameter \"sld_sim_n_scan\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_sim_total_length 0 " "Parameter \"sld_sim_total_length\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_type_id 34 " "Parameter \"sld_type_id\" = \"34\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "sld_version 3 " "Parameter \"sld_version\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584946720 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 206 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1498584946720 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_virtual_jtag_impl NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst " "Elaborating entity \"sld_virtual_jtag_impl\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\"" {  } { { "sld_virtual_jtag_basic.v" "sld_virtual_jtag_impl_inst" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 152 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946720 ""}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy " "Elaborated megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\", which is child of megafunction instantiation \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\"" {  } { { "sld_virtual_jtag_basic.v" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 152 0 0 } } { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper.v" 206 0 0 } }  } 0 12131 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946720 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\|sld_jtag_endpoint_adapter:jtag_signal_adapter " "Elaborating entity \"sld_jtag_endpoint_adapter\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\|sld_jtag_endpoint_adapter:jtag_signal_adapter\"" {  } { { "sld_virtual_jtag_basic.v" "jtag_signal_adapter" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/sld_virtual_jtag_basic.v" 415 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584946938 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_jtag_endpoint_adapter_impl NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst " "Elaborating entity \"sld_jtag_endpoint_adapter_impl\" for hierarchy \"NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper:the_NIOS_LED_nios2_gen2_0_cpu_debug_slave_wrapper\|sld_virtual_jtag_basic:NIOS_LED_nios2_gen2_0_cpu_debug_slave_phy\|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst\|sld_jtag_endpoint_adapter:jtag_signal_adapter\|sld_jtag_endpoint_adapter_impl:sld_jtag_endpoint_adapter_impl_inst\"" {  } { { "sld_jtag_endpoint_adapter.vhd" "sld_jtag_endpoint_adapter_impl_inst" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd" 228 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947251 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_onchip_memory2_0 NIOS_LED_onchip_memory2_0:onchip_memory2_0 " "Elaborating entity \"NIOS_LED_onchip_memory2_0\" for hierarchy \"NIOS_LED_onchip_memory2_0:onchip_memory2_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "onchip_memory2_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 321 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947345 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram " "Elaborating entity \"altsyncram\" for hierarchy \"NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" "the_altsyncram" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" 66 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947360 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram " "Elaborated megafunction instantiation \"NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" 66 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947360 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram " "Instantiated megafunction \"NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file NIOS_LED_onchip_memory2_0.hex " "Parameter \"init_file\" = \"NIOS_LED_onchip_memory2_0.hex\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "maximum_depth 8192 " "Parameter \"maximum_depth\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 8192 " "Parameter \"numwords_a\" = \"8192\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode SINGLE_PORT " "Parameter \"operation_mode\" = \"SINGLE_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type AUTO " "Parameter \"ram_block_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 4 " "Parameter \"width_byteena_a\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 13 " "Parameter \"widthad_a\" = \"13\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1498584947360 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_onchip_memory2_0.v" 66 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1498584947360 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_0hc1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_0hc1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_0hc1 " "Found entity 1: altsyncram_0hc1" {  } { { "db/altsyncram_0hc1.tdf" "" { Text "C:/ALTERA/NIOS_LED/db/altsyncram_0hc1.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584947423 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584947423 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_0hc1 NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram\|altsyncram_0hc1:auto_generated " "Elaborating entity \"altsyncram_0hc1\" for hierarchy \"NIOS_LED_onchip_memory2_0:onchip_memory2_0\|altsyncram:the_altsyncram\|altsyncram_0hc1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947423 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_pio_0 NIOS_LED_pio_0:pio_0 " "Elaborating entity \"NIOS_LED_pio_0\" for hierarchy \"NIOS_LED_pio_0:pio_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "pio_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 335 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947438 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_timer_0 NIOS_LED_timer_0:timer_0 " "Elaborating entity \"NIOS_LED_timer_0\" for hierarchy \"NIOS_LED_timer_0:timer_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "timer_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 347 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947438 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0 NIOS_LED_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"NIOS_LED_mm_interconnect_0\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "mm_interconnect_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 359 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947438 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:nios2_gen2_0_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:nios2_gen2_0_data_master_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_data_master_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 497 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947470 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:nios2_gen2_0_instruction_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:nios2_gen2_0_instruction_master_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_instruction_master_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 557 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947470 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:hex7led_0_avalon_slave_0_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:hex7led_0_avalon_slave_0_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 621 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947470 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:nios2_gen2_0_debug_mem_slave_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:nios2_gen2_0_debug_mem_slave_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_debug_mem_slave_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 685 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:onchip_memory2_0_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:onchip_memory2_0_s1_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "onchip_memory2_0_s1_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 749 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:timer_0_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:timer_0_s1_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "timer_0_s1_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 813 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:pio_0_s1_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:pio_0_s1_translator\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "pio_0_s1_translator" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 877 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:nios2_gen2_0_data_master_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:nios2_gen2_0_data_master_agent\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_data_master_agent" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 958 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:nios2_gen2_0_instruction_master_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:nios2_gen2_0_instruction_master_agent\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_instruction_master_agent" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1039 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:hex7led_0_avalon_slave_0_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:hex7led_0_avalon_slave_0_agent\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_agent" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1123 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:hex7led_0_avalon_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:hex7led_0_avalon_slave_0_agent\|altera_merlin_burst_uncompressor:uncompressor\"" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947501 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_agent_rsp_fifo" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1164 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947517 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:nios2_gen2_0_debug_mem_slave_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:nios2_gen2_0_debug_mem_slave_agent\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_debug_mem_slave_agent" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1248 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947517 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:nios2_gen2_0_debug_mem_slave_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:nios2_gen2_0_debug_mem_slave_agent\|altera_merlin_burst_uncompressor:uncompressor\"" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" "uncompressor" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_slave_agent.sv" 608 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947517 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:nios2_gen2_0_debug_mem_slave_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:nios2_gen2_0_debug_mem_slave_agent_rsp_fifo\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "nios2_gen2_0_debug_mem_slave_agent_rsp_fifo" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1289 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947532 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router:router " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router:router\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "router" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1680 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947548 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_default_decode NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router:router\|NIOS_LED_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_default_decode\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router:router\|NIOS_LED_mm_interconnect_0_router_default_decode:the_default_decode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" "the_default_decode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router.sv" 188 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_001 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_001:router_001 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_001\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_001:router_001\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "router_001" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1696 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_001_default_decode NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_001:router_001\|NIOS_LED_mm_interconnect_0_router_001_default_decode:the_default_decode " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_001_default_decode\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_001:router_001\|NIOS_LED_mm_interconnect_0_router_001_default_decode:the_default_decode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" "the_default_decode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_001.sv" 180 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_002 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_002:router_002 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_002\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_002:router_002\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "router_002" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1712 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947563 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_002_default_decode NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_002:router_002\|NIOS_LED_mm_interconnect_0_router_002_default_decode:the_default_decode " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_002_default_decode\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_002:router_002\|NIOS_LED_mm_interconnect_0_router_002_default_decode:the_default_decode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" "the_default_decode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_002.sv" 173 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_003 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_003:router_003 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_003\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_003:router_003\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "router_003" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1728 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_003_default_decode NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_003:router_003\|NIOS_LED_mm_interconnect_0_router_003_default_decode:the_default_decode " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_003_default_decode\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_003:router_003\|NIOS_LED_mm_interconnect_0_router_003_default_decode:the_default_decode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" "the_default_decode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_003.sv" 178 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_005 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_005:router_005 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_005\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_005:router_005\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "router_005" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1760 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947579 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_router_005_default_decode NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_005:router_005\|NIOS_LED_mm_interconnect_0_router_005_default_decode:the_default_decode " "Elaborating entity \"NIOS_LED_mm_interconnect_0_router_005_default_decode\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_router_005:router_005\|NIOS_LED_mm_interconnect_0_router_005_default_decode:the_default_decode\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" "the_default_decode" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_router_005.sv" 173 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:hex7led_0_avalon_slave_0_burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:hex7led_0_avalon_slave_0_burst_adapter\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_burst_adapter" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1826 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_adapter_uncompressed_only NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:hex7led_0_avalon_slave_0_burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.burst_adapter " "Elaborating entity \"altera_merlin_burst_adapter_uncompressed_only\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_burst_adapter:hex7led_0_avalon_slave_0_burst_adapter\|altera_merlin_burst_adapter_uncompressed_only:altera_merlin_burst_adapter_uncompressed_only.burst_adapter\"" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter.sv" "altera_merlin_burst_adapter_uncompressed_only.burst_adapter" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_burst_adapter.sv" 126 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_cmd_demux NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"NIOS_LED_mm_interconnect_0_cmd_demux\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_demux:cmd_demux\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "cmd_demux" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1867 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947610 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_cmd_demux_001 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_demux_001:cmd_demux_001 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_cmd_demux_001\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_demux_001:cmd_demux_001\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "cmd_demux_001" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1890 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947610 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_cmd_mux NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"NIOS_LED_mm_interconnect_0_cmd_mux\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux:cmd_mux\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "cmd_mux" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1907 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947610 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_cmd_mux_001 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_cmd_mux_001\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "cmd_mux_001" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 1930 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947610 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001\|altera_merlin_arbitrator:arb\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux_001.sv" "arb" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_cmd_mux_001.sv" 287 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947626 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_cmd_mux_001:cmd_mux_001\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947626 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_rsp_demux NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"NIOS_LED_mm_interconnect_0_rsp_demux\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_demux:rsp_demux\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "rsp_demux" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2004 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947642 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_rsp_mux NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"NIOS_LED_mm_interconnect_0_rsp_mux\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "rsp_mux" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2125 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947642 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux.sv" "arb" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux.sv" 358 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947657 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" "adder" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947657 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_rsp_mux_001 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux_001:rsp_mux_001 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_rsp_mux_001\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux_001:rsp_mux_001\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "rsp_mux_001" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2148 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947657 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux_001:rsp_mux_001\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_rsp_mux_001:rsp_mux_001\|altera_merlin_arbitrator:arb\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux_001.sv" "arb" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_rsp_mux_001.sv" 310 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947657 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_rsp_width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_rsp_width_adapter\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_rsp_width_adapter" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2214 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947673 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "in_write altera_merlin_width_adapter.sv(283) " "Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(283): object \"in_write\" assigned a value but never read" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 283 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1498584947673 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_rsp_width_adapter"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aligned_addr altera_merlin_width_adapter.sv(742) " "Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(742): object \"aligned_addr\" assigned a value but never read" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 742 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1498584947673 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_rsp_width_adapter"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "aligned_byte_cnt altera_merlin_width_adapter.sv(743) " "Verilog HDL or VHDL warning at altera_merlin_width_adapter.sv(743): object \"aligned_byte_cnt\" assigned a value but never read" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 743 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1498584947673 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_rsp_width_adapter"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_width_adapter NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter " "Elaborating entity \"altera_merlin_width_adapter\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "hex7led_0_avalon_slave_0_cmd_width_adapter" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2280 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947673 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_avalon_st_adapter NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"NIOS_LED_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "avalon_st_adapter" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2309 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_avalon_st_adapter_001 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001:avalon_st_adapter_001 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_avalon_st_adapter_001\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001:avalon_st_adapter_001\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" "avalon_st_adapter_001" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0.v" 2338 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001:avalon_st_adapter_001\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0:error_adapter_0 " "Elaborating entity \"NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0\" for hierarchy \"NIOS_LED_mm_interconnect_0:mm_interconnect_0\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001:avalon_st_adapter_001\|NIOS_LED_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0:error_adapter_0\"" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001.v" "error_adapter_0" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_mm_interconnect_0_avalon_st_adapter_001.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NIOS_LED_irq_mapper NIOS_LED_irq_mapper:irq_mapper " "Elaborating entity \"NIOS_LED_irq_mapper\" for hierarchy \"NIOS_LED_irq_mapper:irq_mapper\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "irq_mapper" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 406 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947704 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_controller altera_reset_controller:rst_controller " "Elaborating entity \"altera_reset_controller\" for hierarchy \"altera_reset_controller:rst_controller\"" {  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "rst_controller" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 414 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947704 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_sync_uq1\"" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "alt_rst_sync_uq1" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 208 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947720 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_reset_synchronizer altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1 " "Elaborating entity \"altera_reset_synchronizer\" for hierarchy \"altera_reset_controller:rst_controller\|altera_reset_synchronizer:alt_rst_req_sync_uq1\"" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "alt_rst_req_sync_uq1" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 220 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584947720 ""}
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "sld_hub " "Start IP generation for the debug fabric within sld_hub." {  } {  } 0 11170 "Start IP generation for the debug fabric within %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1498584949188 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2017.06.27.19:35:54 Progress: Loading sld68f8d15f/alt_sld_fab_wrapper_hw.tcl " "2017.06.27.19:35:54 Progress: Loading sld68f8d15f/alt_sld_fab_wrapper_hw.tcl" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584954188 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584957079 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584957298 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584959425 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584959707 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584959988 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584960285 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584960316 ""}
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" {  } {  } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584960316 ""}
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "sld_hub " "Finished IP generation for the debug fabric within sld_hub." {  } {  } 0 11171 "Finished IP generation for the debug fabric within %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1498584961066 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld68f8d15f/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" {  } { { "db/ip/sld68f8d15f/alt_sld_fab.v" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584961613 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584961613 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584961832 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584961832 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584961832 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584961832 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584962019 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584962019 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 93 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584962238 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584962238 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584962238 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" {  } { { "db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "C:/ALTERA/NIOS_LED/db/ip/sld68f8d15f/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1498584962425 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584962425 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1498584968253 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[4\] " "Latch x7seg:hex7led_0\|x_sig\[4\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[8\] " "Latch x7seg:hex7led_0\|x_sig\[8\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[0\] " "Latch x7seg:hex7led_0\|x_sig\[0\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[12\] " "Latch x7seg:hex7led_0\|x_sig\[12\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[9\] " "Latch x7seg:hex7led_0\|x_sig\[9\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[5\] " "Latch x7seg:hex7led_0\|x_sig\[5\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[1\] " "Latch x7seg:hex7led_0\|x_sig\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[13\] " "Latch x7seg:hex7led_0\|x_sig\[13\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[6\] " "Latch x7seg:hex7led_0\|x_sig\[6\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[10\] " "Latch x7seg:hex7led_0\|x_sig\[10\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[2\] " "Latch x7seg:hex7led_0\|x_sig\[2\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[14\] " "Latch x7seg:hex7led_0\|x_sig\[14\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[11\] " "Latch x7seg:hex7led_0\|x_sig\[11\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[7\] " "Latch x7seg:hex7led_0\|x_sig\[7\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[3\] " "Latch x7seg:hex7led_0\|x_sig\[3\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "x7seg:hex7led_0\|x_sig\[15\] " "Latch x7seg:hex7led_0\|x_sig\[15\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg " "Ports D and ENA on the latch are fed by the same signal NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_merlin_width_adapter:hex7led_0_avalon_slave_0_cmd_width_adapter\|use_reg" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_width_adapter.sv" 308 -1 0 } }  } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1498584968425 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } }  } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1498584968425 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "NIOS_LED/synthesis/submodules/altera_merlin_master_agent.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_master_agent.sv" 239 -1 0 } } { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2867 -1 0 } } { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 3867 -1 0 } } { "NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_merlin_arbitrator.sv" 203 -1 0 } } { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 3488 -1 0 } } { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 2084 -1 0 } } { "NIOS_LED/synthesis/submodules/altera_reset_synchronizer.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_synchronizer.v" 62 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1498584968441 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1498584968441 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584969410 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "97 " "97 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1498584971316 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "sld_jtag_hub.vhd" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/sld_jtag_hub.vhd" 373 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1498584971660 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1498584971660 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "sld_hub:auto_hub " "Timing-Driven Synthesis is running on partition \"sld_hub:auto_hub\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584971816 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/ALTERA/NIOS_LED/output_files/NIOS_LED.map.smsg " "Generated suppressed messages file C:/ALTERA/NIOS_LED/output_files/NIOS_LED.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584973175 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1498584976550 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1498584976550 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1828 " "Implemented 1828 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1498584978097 ""} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Implemented 17 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1498584978097 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1678 " "Implemented 1678 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1498584978097 ""} { "Info" "ICUT_CUT_TM_RAMS" "128 " "Implemented 128 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1498584978097 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1498584978097 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 42 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 42 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "972 " "Peak virtual memory: 972 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498584978222 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 19:36:18 2017 " "Processing ended: Tue Jun 27 19:36:18 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498584978222 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:45 " "Elapsed time: 00:00:45" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498584978222 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:11 " "Total CPU time (on all processors): 00:01:11" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498584978222 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1498584978222 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1498584981863 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498584981863 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 19:36:19 2017 " "Processing started: Tue Jun 27 19:36:19 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498584981863 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1498584981863 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED " "Command: quartus_fit --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1498584981863 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" {  } {  } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1498584982082 ""}
{ "Info" "0" "" "Project  = NIOS_LED" {  } {  } 0 0 "Project  = NIOS_LED" 0 0 "Fitter" 0 0 1498584982082 ""}
{ "Info" "0" "" "Revision = NIOS_LED" {  } {  } 0 0 "Revision = NIOS_LED" 0 0 "Fitter" 0 0 1498584982082 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1498584982363 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1498584982363 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "NIOS_LED 10M08DAF256C8GES " "Selected device 10M08DAF256C8GES for design \"NIOS_LED\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1498584982425 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1498584982582 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1498584982582 ""}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1498584983035 ""}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1498584983129 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M08DAF256C8G " "Device 10M08DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M04DAF256C8G " "Device 10M04DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M16DAF256C8G " "Device 10M16DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M25DAF256C8G " "Device 10M25DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF256C8GES " "Device 10M50DAF256C8GES is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M50DAF256C8G " "Device 10M50DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "10M40DAF256C8G " "Device 10M40DAF256C8G is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1498584984019 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1498584984019 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONFIG_SEL~ F8 " "Pin ~ALTERA_CONFIG_SEL~ is reserved at location F8" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONFIG_SEL~ } } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "~ALTERA_CONFIG_SEL~" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 194 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1498584984082 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCONFIG~ E8 " "Pin ~ALTERA_nCONFIG~ is reserved at location E8" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCONFIG~ } } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "~ALTERA_nCONFIG~" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 196 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1498584984082 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nSTATUS~ F7 " "Pin ~ALTERA_nSTATUS~ is reserved at location F7" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nSTATUS~ } } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "~ALTERA_nSTATUS~" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 197 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1498584984082 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_CONF_DONE~ E7 " "Pin ~ALTERA_CONF_DONE~ is reserved at location E7" {  } { { "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera_lite/16.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_CONF_DONE~ } } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "~ALTERA_CONF_DONE~" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 195 14046 14942 0 0 ""}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1498584984082 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1498584984082 ""}
{ "Info" "IFIOMGR_RESERVE_PIN_NO_DATA0" "" "DATA\[0\] dual-purpose pin not reserved" {  } {  } 0 169141 "DATA\[0\] dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1498584984082 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "Data\[1\]/ASDO " "Data\[1\]/ASDO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1498584984082 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "nCSO " "nCSO dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1498584984082 ""}
{ "Info" "IFIOMGR_PIN_NOT_RESERVE" "DCLK " "DCLK dual-purpose pin not reserved" {  } {  } 0 12825 "%1!s! dual-purpose pin not reserved" 0 0 "Fitter" 0 -1 1498584984082 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1498584984113 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1498584984191 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "12 17 " "No exact pin location assignment(s) for 12 pins of 17 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." {  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1498584984785 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "TimeQuest Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1498584985957 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498584985957 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498584985957 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498584985957 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498584985957 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498584985957 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1498584985957 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1498584985988 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1498584985988 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498584986019 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1498584986019 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[12\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[12\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498584986019 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1498584986019 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498584986019 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1498584986019 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498584986050 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498584986050 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1498584986050 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1498584986050 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1498584986066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1498584986066 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" {  } {  } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1498584986066 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1498584986066 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L18p, DIFFOUT_L18p, High_Speed)) " "Automatically promoted node clk_clk~input (placed in PIN L3 (CLK0p, DIFFIO_RX_L18p, DIFFOUT_L18p, High_Speed))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G4 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G4" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "NIOS_LED/synthesis/NIOS_LED.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/NIOS_LED.vhd" 11 0 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5695 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP  " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 5333 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "x7seg:hex7led_0\|be\[0\]~1  " "Automatically promoted node x7seg:hex7led_0\|be\[0\]~1 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 26 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 2175 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "x7seg:hex7led_0\|be\[1\]~2  " "Automatically promoted node x7seg:hex7led_0\|be\[1\]~2 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 26 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 2177 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_reset_controller:rst_controller\|r_sync_rst  " "Automatically promoted node altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node altera_reset_controller:rst_controller\|WideOr0~0" {  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 290 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 2192 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|W_rf_wren " "Destination node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|W_rf_wren" {  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 3440 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1611 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1 " "Destination node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" {  } { { "altera_std_synchronizer.v" "" { Text "c:/altera_lite/16.0/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 859 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[4\] " "Destination node x7seg:hex7led_0\|x_sig\[4\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1729 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[8\] " "Destination node x7seg:hex7led_0\|x_sig\[8\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1733 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[0\] " "Destination node x7seg:hex7led_0\|x_sig\[0\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1726 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[12\] " "Destination node x7seg:hex7led_0\|x_sig\[12\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1737 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[9\] " "Destination node x7seg:hex7led_0\|x_sig\[9\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1734 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[5\] " "Destination node x7seg:hex7led_0\|x_sig\[5\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1730 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "x7seg:hex7led_0\|x_sig\[1\] " "Destination node x7seg:hex7led_0\|x_sig\[1\]" {  } { { "NIOS_LED/synthesis/submodules/x7seg.vhd" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/x7seg.vhd" 55 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 1723 14046 14942 0 0 ""}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1498584986332 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Non-global destination nodes limited to 10 nodes" {  } {  } 0 176358 "Non-global destination nodes limited to %1!d! nodes" 0 0 "Design Software" 0 -1 1498584986332 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "NIOS_LED/synthesis/submodules/altera_reset_controller.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/altera_reset_controller.v" 288 -1 0 } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 216 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest  " "Automatically promoted node NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1498584986332 ""}  } { { "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" "" { Text "C:/ALTERA/NIOS_LED/NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.v" 184 -1 0 } } { "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera_lite/16.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci\|NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug:the_NIOS_LED_nios2_gen2_0_cpu_nios2_oci_debug\|resetrequest" } } } } { "temporary_test_loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 0 { 0 ""} 0 864 14046 14942 0 0 ""}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1498584986332 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1498584987129 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1498584987129 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1498584987129 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1498584987144 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1498584987144 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1498584987160 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1498584987160 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1498584987160 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1498584987222 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1498584987222 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1498584987222 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "12 unused 2.5V 0 12 0 " "Number of I/O pins in group: 12 (unused VREF, 2.5V VCCIO, 0 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1498584987269 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1498584987269 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1498584987269 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1A does not use undetermined 0 16 " "I/O bank number 1A does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  16 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1B does not use undetermined 4 6 " "I/O bank number 1B does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  6 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 15 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  15 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 32 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  32 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 12 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 2.5V 4 16 " "I/O bank number 5 does not use VREF pins and has 2.5V VCCIO pins. 4 total pin(s) used --  16 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 28 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 12 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  12 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 4 28 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 4 total pin(s) used --  28 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Design Software" 0 -1 1498584987269 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1498584987269 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1498584987269 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1498584987394 ""}
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." {  } {  } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1498584987535 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1498584988800 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1498584989285 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1498584989410 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1498584990238 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1498584990238 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1498584991175 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "12 X10_Y0 X20_Y12 " "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12" {  } { { "loc" "" { Generic "C:/ALTERA/NIOS_LED/" { { 1 { 0 "Router estimated peak interconnect usage is 12% of the available device resources in the region that extends from location X10_Y0 to location X20_Y12"} { { 12 { 0 ""} 10 0 11 13 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1498584992363 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1498584992363 ""}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" {  } {  } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1498584992582 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" {  } {  } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1498584992582 ""}  } {  } 0 170199 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1498584992582 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1498584992597 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.35 " "Total time spent on timing analysis during the Fitter is 0.35 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1498584992894 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1498584992925 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1498584992925 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1498584994097 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1498584994097 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Fitter" 0 -1 1498584994097 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1498584995504 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:04 " "Fitter post-fit operations ending: elapsed time is 00:00:04" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1498584996457 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[0\] 2.5 V C10 " "Pin hex7led_0_segment_new_signal\[0\] uses I/O standard 2.5 V located at C10 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[1\] 2.5 V B10 " "Pin hex7led_0_segment_new_signal\[1\] uses I/O standard 2.5 V located at B10 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[3\] 2.5 V B8 " "Pin hex7led_0_segment_new_signal\[3\] uses I/O standard 2.5 V located at B8 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[4\] 2.5 V E9 " "Pin hex7led_0_segment_new_signal\[4\] uses I/O standard 2.5 V located at E9 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[5\] 2.5 V F9 " "Pin hex7led_0_segment_new_signal\[5\] uses I/O standard 2.5 V located at F9 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Warning" "WFIOMGR_LOW_SPEED_IO_PLACEMENT_WARNING" "hex7led_0_segment_new_signal\[6\] 2.5 V C4 " "Pin hex7led_0_segment_new_signal\[6\] uses I/O standard 2.5 V located at C4 will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." {  } {  } 0 14579 "Pin %1!s! uses I/O standard %2!s! located at %3!s! will have lower speed performance due to its location.  Refer to the product datasheet for the supported I/O speed." 0 0 "Fitter" 0 -1 1498584996785 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/ALTERA/NIOS_LED/output_files/NIOS_LED.fit.smsg " "Generated suppressed messages file C:/ALTERA/NIOS_LED/output_files/NIOS_LED.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1498584997082 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 18 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1746 " "Peak virtual memory: 1746 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498584998675 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 19:36:38 2017 " "Processing ended: Tue Jun 27 19:36:38 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498584998675 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498584998675 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498584998675 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1498584998675 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1498585001425 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498585001425 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 19:36:41 2017 " "Processing started: Tue Jun 27 19:36:41 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498585001425 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1498585001425 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED " "Command: quartus_asm --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1498585001425 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1498585002035 ""}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" {  } {  } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1498585003879 ""}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" {  } {  } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1498585003925 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1  Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "787 " "Peak virtual memory: 787 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498585004566 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 19:36:44 2017 " "Processing ended: Tue Jun 27 19:36:44 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498585004566 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498585004566 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498585004566 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1498585004566 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1498585005488 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1498585006504 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498585006504 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 19:36:45 2017 " "Processing started: Tue Jun 27 19:36:45 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498585006504 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585006504 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta NIOS_LED -c NIOS_LED " "Command: quartus_sta NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585006504 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1498585006800 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007191 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007191 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007269 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007269 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "TimeQuest Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007519 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498585007613 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498585007613 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498585007613 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498585007613 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498585007613 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007613 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007629 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007644 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585007660 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007660 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585007660 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007660 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498585007660 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007660 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585007675 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585007675 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007675 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1498585007691 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498585007754 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1498585007754 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 45.995 " "Worst-case setup slack is 45.995" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   45.995               0.000 altera_reserved_tck  " "   45.995               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007769 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.360               0.000 altera_reserved_tck  " "    0.360               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007769 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007769 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 97.781 " "Worst-case recovery slack is 97.781" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.781               0.000 altera_reserved_tck  " "   97.781               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007785 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.533 " "Worst-case removal slack is 1.533" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.533               0.000 altera_reserved_tck  " "    1.533               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007785 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007785 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.658 " "Worst-case minimum pulse width slack is 49.658" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007800 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.658               0.000 altera_reserved_tck  " "   49.658               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585007800 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007800 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 196.907 ns " "Worst Case Available Settling Time: 196.907 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585007816 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007816 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498585007894 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007957 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585007957 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009644 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585009910 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009910 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585009910 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009910 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498585009910 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009910 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585009910 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585009910 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009910 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.168 " "Worst-case setup slack is 46.168" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.168               0.000 altera_reserved_tck  " "   46.168               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009925 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.322               0.000 altera_reserved_tck  " "    0.322               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009925 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009925 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 97.908 " "Worst-case recovery slack is 97.908" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.908               0.000 altera_reserved_tck  " "   97.908               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009941 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.368 " "Worst-case removal slack is 1.368" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.368               0.000 altera_reserved_tck  " "    1.368               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009941 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009941 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.678 " "Worst-case minimum pulse width slack is 49.678" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009957 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009957 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.678               0.000 altera_reserved_tck  " "   49.678               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585009957 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009957 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.127 ns " "Worst Case Available Settling Time: 197.127 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585009972 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585009972 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498585009988 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585010254 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010254 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498585010254 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010254 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498585010254 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010254 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585010254 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498585010254 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010254 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.771 " "Worst-case setup slack is 48.771" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010254 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.771               0.000 altera_reserved_tck  " "   48.771               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010254 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010254 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.151 " "Worst-case hold slack is 0.151" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.151               0.000 altera_reserved_tck  " "    0.151               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010269 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 99.044 " "Worst-case recovery slack is 99.044" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   99.044               0.000 altera_reserved_tck  " "   99.044               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010269 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010269 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.616 " "Worst-case removal slack is 0.616" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.616               0.000 altera_reserved_tck  " "    0.616               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010285 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.421 " "Worst-case minimum pulse width slack is 49.421" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.421               0.000 altera_reserved_tck  " "   49.421               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498585010285 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010285 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.798 ns " "Worst Case Available Settling Time: 198.798 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498585010300 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585010300 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585011332 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585011332 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 18 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "928 " "Peak virtual memory: 928 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498585011472 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 19:36:51 2017 " "Processing ended: Tue Jun 27 19:36:51 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498585011472 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498585011472 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498585011472 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585011472 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498585013238 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498585013238 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 19:36:53 2017 " "Processing started: Tue Jun 27 19:36:53 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498585013238 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1498585013238 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED " "Command: quartus_eda --read_settings_files=off --write_settings_files=off NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1498585013238 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1498585013972 ""}
{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." {  } {  } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1498585014988 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "NIOS_LED.vho C:/ALTERA/NIOS_LED/simulation/modelsim/ simulation " "Generated file NIOS_LED.vho in folder \"C:/ALTERA/NIOS_LED/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1498585015754 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "788 " "Peak virtual memory: 788 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498585017738 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 19:36:57 2017 " "Processing ended: Tue Jun 27 19:36:57 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498585017738 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498585017738 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498585017738 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1498585017738 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 81 s " "Quartus Prime Full Compilation was successful. 0 errors, 81 warnings" {  } {  } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1498585018441 ""}
