{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1474823637818 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "PowerPlay Power Analyzer Quartus Prime " "Running Quartus Prime PowerPlay Power Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1474823637824 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 25 19:13:57 2016 " "Processing started: Sun Sep 25 19:13:57 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1474823637824 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823637824 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_pow --read_settings_files=on --write_settings_files=off NIOS_LED -c NIOS_LED " "Command: quartus_pow --read_settings_files=on --write_settings_files=off NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823637825 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "PowerPlay Power Analyzer" 0 -1 1474823638722 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823638776 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823638776 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1474823639416 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1474823639416 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1474823639416 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1474823639416 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1474823639416 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639416 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639431 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639438 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639442 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|hbreak_enabled clk_clk " "Register NIOS_LED_nios2_gen2_0:nios2_gen2_0\|NIOS_LED_nios2_gen2_0_cpu:cpu\|hbreak_enabled is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1474823639461 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639461 "|NIOS_LED|clk_clk"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1474823639461 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639461 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: altpll_0\|sd1\|pll7\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000 " "Node: altpll_0\|sd1\|pll7\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000" {  } {  } 0 332056 "%1!s!" 0 0 "Design Software" 0 -1 1474823639480 ""}  } {  } 0 332056 "%1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639480 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1474823639481 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1474823639481 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639481 ""}
{ "Info" "IPVA_PVA_START_CALCULATION" "" "Starting Vectorless Power Activity Estimation" {  } {  } 0 223000 "Starting Vectorless Power Activity Estimation" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639514 ""}
{ "Warning" "WPUTIL_PUTIL_NO_CLK_DOMAINS_FOUND" "" "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" {  } {  } 0 222013 "Relative toggle rates could not be calculated because no clock domain could be identified for some nodes" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639549 ""}
{ "Info" "IPVA_PVA_END_CALCULATION" "" "Completed Vectorless Power Activity Estimation" {  } {  } 0 223001 "Completed Vectorless Power Activity Estimation" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639578 ""}
{ "Info" "IPATFAM_USING_ADVANCED_IO_POWER" "" "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" {  } {  } 0 218000 "Using Advanced I/O Power to simulate I/O buffers with the specified board trace model" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823639958 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823640128 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823640129 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823641549 ""}
{ "Info" "IPAN_AVG_TOGGLE_RATE_PER_DESIGN" "0.200 millions of transitions / sec " "Average toggle rate for this design is 0.200 millions of transitions / sec" {  } {  } 0 215049 "Average toggle rate for this design is %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823647128 ""}
{ "Info" "IPAN_PAN_TOTAL_POWER_ESTIMATION" "52.24 mW " "Total thermal power estimate for the design is 52.24 mW" {  } { { "c:/altera_lite/16.0/quartus/bin64/Report_Window_01.qrpt" "" { Report "c:/altera_lite/16.0/quartus/bin64/Report_Window_01.qrpt" "Compiler" "" "" "" "" { } "PowerPlay Power Analyzer Summary" } }  } 0 215031 "Total thermal power estimate for the design is %1!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823647183 ""}
{ "Info" "IQEXE_ERROR_COUNT" "PowerPlay Power Analyzer 0 s 9 s Quartus Prime " "Quartus Prime PowerPlay Power Analyzer was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "952 " "Peak virtual memory: 952 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1474823647565 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 25 19:14:07 2016 " "Processing ended: Sun Sep 25 19:14:07 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1474823647565 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1474823647565 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1474823647565 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "PowerPlay Power Analyzer" 0 -1 1474823647565 ""}
