--altsyncram BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="MAX 10" INIT_FILE="NIOS_LED_onchip_memory2_0.hex" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=65536 NUMWORDS_A=65536 OPERATION_MODE="SINGLE_PORT" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=32 WIDTH_BYTEENA_A=4 WIDTHAD_A=16 address_a byteena_a clock0 clocken0 data_a q_a wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 16.0 cbx_altera_syncram_nd_impl 2016:04:27:18:05:34:SJ cbx_altsyncram 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ  VERSION_END


-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, the Altera Quartus Prime License Agreement,
--  the Altera MegaCore Function License Agreement, or other 
--  applicable license agreement, including, without limitation, 
--  that your use is for the sole purpose of programming logic 
--  devices manufactured by Altera and sold by Altera or its 
--  authorized distributors.  Please refer to the applicable 
--  agreement for further details.


FUNCTION decode_h7a (data[2..0], enable)
RETURNS ( eq[7..0]);
FUNCTION mux_e3b (data[255..0], sel[2..0])
RETURNS ( result[31..0]);
FUNCTION fiftyfivenm_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = lut 168 M9K 256 reg 3 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_dkc1
( 
	address_a[15..0]	:	input;
	byteena_a[3..0]	:	input;
	clock0	:	input;
	clocken0	:	input;
	data_a[31..0]	:	input;
	q_a[31..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	address_reg_a[2..0] : dffe;
	decode3 : decode_h7a;
	mux2 : mux_e3b;
	ram_block1a0 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a1 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a2 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a3 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a4 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a5 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a6 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a7 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a8 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a9 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a10 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a11 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a12 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a13 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a14 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a15 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a16 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a17 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a18 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a19 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a20 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a21 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a22 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a23 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a24 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a25 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a26 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a27 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a28 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a29 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a30 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a31 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 8191,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a32 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a33 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a34 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a35 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a36 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a37 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a38 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a39 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a40 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a41 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a42 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a43 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a44 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a45 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a46 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a47 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a48 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a49 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a50 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a51 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a52 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a53 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a54 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a55 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a56 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a57 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a58 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a59 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a60 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a61 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a62 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a63 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 8192,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a64 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a65 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a66 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a67 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a68 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a69 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a70 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a71 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a72 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a73 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a74 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a75 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a76 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a77 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a78 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a79 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a80 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a81 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a82 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a83 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a84 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a85 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a86 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a87 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a88 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a89 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a90 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a91 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a92 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a93 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a94 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a95 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 16384,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 24575,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a96 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a97 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a98 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a99 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a100 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a101 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a102 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a103 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a104 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a105 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a106 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a107 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a108 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a109 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a110 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a111 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a112 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a113 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a114 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a115 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a116 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a117 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a118 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a119 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a120 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a121 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a122 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a123 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a124 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a125 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a126 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a127 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 24576,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 32767,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a128 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a129 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a130 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a131 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a132 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a133 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a134 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a135 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a136 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a137 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a138 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a139 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a140 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a141 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a142 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a143 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a144 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a145 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a146 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a147 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a148 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a149 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a150 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a151 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a152 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a153 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a154 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a155 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a156 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a157 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a158 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a159 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 32768,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 40959,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a160 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a161 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a162 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a163 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a164 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a165 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a166 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a167 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a168 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a169 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a170 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a171 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a172 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a173 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a174 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a175 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a176 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a177 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a178 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a179 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a180 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a181 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a182 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a183 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a184 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a185 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a186 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a187 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a188 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a189 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a190 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a191 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 40960,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 49151,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a192 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a193 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a194 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a195 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a196 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a197 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a198 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a199 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a200 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a201 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a202 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a203 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a204 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a205 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a206 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a207 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a208 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a209 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a210 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a211 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a212 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a213 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a214 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a215 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a216 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a217 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a218 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a219 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a220 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a221 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a222 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a223 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 49152,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 57343,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a224 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a225 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a226 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a227 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a228 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a229 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a230 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a231 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a232 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a233 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a234 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a235 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a236 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a237 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a238 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a239 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a240 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a241 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a242 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a243 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a244 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a245 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a246 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a247 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a248 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a249 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a250 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a251 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a252 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a253 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a254 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a255 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "ena0",
			CONNECTIVITY_CHECKING = "OFF",
			INIT_FILE = "NIOS_LED_onchip_memory2_0.hex",
			INIT_FILE_LAYOUT = "port_a",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			OPERATION_MODE = "single_port",
			PORT_A_ADDRESS_WIDTH = 13,
			PORT_A_BYTE_ENABLE_MASK_WIDTH = 1,
			PORT_A_BYTE_SIZE = 1,
			PORT_A_DATA_OUT_CLEAR = "none",
			PORT_A_DATA_OUT_CLOCK = "none",
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 57344,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 65535,
			PORT_A_LOGICAL_RAM_DEPTH = 65536,
			PORT_A_LOGICAL_RAM_WIDTH = 32,
			PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_sel[2..0]	: WIRE;
	address_a_wire[15..0]	: WIRE;

BEGIN 
	address_reg_a[].clk = clock0;
	address_reg_a[].d = address_a_sel[];
	address_reg_a[].ena = clocken0;
	decode3.data[2..0] = address_a_wire[15..13];
	decode3.enable = wren_a;
	mux2.data[] = ( ram_block1a[255..0].portadataout[0..0]);
	mux2.sel[] = address_reg_a[].q;
	ram_block1a[255..0].clk0 = clock0;
	ram_block1a[255..0].ena0 = clocken0;
	ram_block1a[255..0].portaaddr[] = ( address_a_wire[12..0]);
	ram_block1a[7..0].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[15..8].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[23..16].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[31..24].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[39..32].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[47..40].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[55..48].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[63..56].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[71..64].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[79..72].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[87..80].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[95..88].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[103..96].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[111..104].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[119..112].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[127..120].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[135..128].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[143..136].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[151..144].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[159..152].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[167..160].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[175..168].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[183..176].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[191..184].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[199..192].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[207..200].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[215..208].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[223..216].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[231..224].portabyteenamasks[] = ( byteena_a[0..0]);
	ram_block1a[239..232].portabyteenamasks[] = ( byteena_a[1..1]);
	ram_block1a[247..240].portabyteenamasks[] = ( byteena_a[2..2]);
	ram_block1a[255..248].portabyteenamasks[] = ( byteena_a[3..3]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[16..16]);
	ram_block1a[17].portadatain[] = ( data_a[17..17]);
	ram_block1a[18].portadatain[] = ( data_a[18..18]);
	ram_block1a[19].portadatain[] = ( data_a[19..19]);
	ram_block1a[20].portadatain[] = ( data_a[20..20]);
	ram_block1a[21].portadatain[] = ( data_a[21..21]);
	ram_block1a[22].portadatain[] = ( data_a[22..22]);
	ram_block1a[23].portadatain[] = ( data_a[23..23]);
	ram_block1a[24].portadatain[] = ( data_a[24..24]);
	ram_block1a[25].portadatain[] = ( data_a[25..25]);
	ram_block1a[26].portadatain[] = ( data_a[26..26]);
	ram_block1a[27].portadatain[] = ( data_a[27..27]);
	ram_block1a[28].portadatain[] = ( data_a[28..28]);
	ram_block1a[29].portadatain[] = ( data_a[29..29]);
	ram_block1a[30].portadatain[] = ( data_a[30..30]);
	ram_block1a[31].portadatain[] = ( data_a[31..31]);
	ram_block1a[32].portadatain[] = ( data_a[0..0]);
	ram_block1a[33].portadatain[] = ( data_a[1..1]);
	ram_block1a[34].portadatain[] = ( data_a[2..2]);
	ram_block1a[35].portadatain[] = ( data_a[3..3]);
	ram_block1a[36].portadatain[] = ( data_a[4..4]);
	ram_block1a[37].portadatain[] = ( data_a[5..5]);
	ram_block1a[38].portadatain[] = ( data_a[6..6]);
	ram_block1a[39].portadatain[] = ( data_a[7..7]);
	ram_block1a[40].portadatain[] = ( data_a[8..8]);
	ram_block1a[41].portadatain[] = ( data_a[9..9]);
	ram_block1a[42].portadatain[] = ( data_a[10..10]);
	ram_block1a[43].portadatain[] = ( data_a[11..11]);
	ram_block1a[44].portadatain[] = ( data_a[12..12]);
	ram_block1a[45].portadatain[] = ( data_a[13..13]);
	ram_block1a[46].portadatain[] = ( data_a[14..14]);
	ram_block1a[47].portadatain[] = ( data_a[15..15]);
	ram_block1a[48].portadatain[] = ( data_a[16..16]);
	ram_block1a[49].portadatain[] = ( data_a[17..17]);
	ram_block1a[50].portadatain[] = ( data_a[18..18]);
	ram_block1a[51].portadatain[] = ( data_a[19..19]);
	ram_block1a[52].portadatain[] = ( data_a[20..20]);
	ram_block1a[53].portadatain[] = ( data_a[21..21]);
	ram_block1a[54].portadatain[] = ( data_a[22..22]);
	ram_block1a[55].portadatain[] = ( data_a[23..23]);
	ram_block1a[56].portadatain[] = ( data_a[24..24]);
	ram_block1a[57].portadatain[] = ( data_a[25..25]);
	ram_block1a[58].portadatain[] = ( data_a[26..26]);
	ram_block1a[59].portadatain[] = ( data_a[27..27]);
	ram_block1a[60].portadatain[] = ( data_a[28..28]);
	ram_block1a[61].portadatain[] = ( data_a[29..29]);
	ram_block1a[62].portadatain[] = ( data_a[30..30]);
	ram_block1a[63].portadatain[] = ( data_a[31..31]);
	ram_block1a[64].portadatain[] = ( data_a[0..0]);
	ram_block1a[65].portadatain[] = ( data_a[1..1]);
	ram_block1a[66].portadatain[] = ( data_a[2..2]);
	ram_block1a[67].portadatain[] = ( data_a[3..3]);
	ram_block1a[68].portadatain[] = ( data_a[4..4]);
	ram_block1a[69].portadatain[] = ( data_a[5..5]);
	ram_block1a[70].portadatain[] = ( data_a[6..6]);
	ram_block1a[71].portadatain[] = ( data_a[7..7]);
	ram_block1a[72].portadatain[] = ( data_a[8..8]);
	ram_block1a[73].portadatain[] = ( data_a[9..9]);
	ram_block1a[74].portadatain[] = ( data_a[10..10]);
	ram_block1a[75].portadatain[] = ( data_a[11..11]);
	ram_block1a[76].portadatain[] = ( data_a[12..12]);
	ram_block1a[77].portadatain[] = ( data_a[13..13]);
	ram_block1a[78].portadatain[] = ( data_a[14..14]);
	ram_block1a[79].portadatain[] = ( data_a[15..15]);
	ram_block1a[80].portadatain[] = ( data_a[16..16]);
	ram_block1a[81].portadatain[] = ( data_a[17..17]);
	ram_block1a[82].portadatain[] = ( data_a[18..18]);
	ram_block1a[83].portadatain[] = ( data_a[19..19]);
	ram_block1a[84].portadatain[] = ( data_a[20..20]);
	ram_block1a[85].portadatain[] = ( data_a[21..21]);
	ram_block1a[86].portadatain[] = ( data_a[22..22]);
	ram_block1a[87].portadatain[] = ( data_a[23..23]);
	ram_block1a[88].portadatain[] = ( data_a[24..24]);
	ram_block1a[89].portadatain[] = ( data_a[25..25]);
	ram_block1a[90].portadatain[] = ( data_a[26..26]);
	ram_block1a[91].portadatain[] = ( data_a[27..27]);
	ram_block1a[92].portadatain[] = ( data_a[28..28]);
	ram_block1a[93].portadatain[] = ( data_a[29..29]);
	ram_block1a[94].portadatain[] = ( data_a[30..30]);
	ram_block1a[95].portadatain[] = ( data_a[31..31]);
	ram_block1a[96].portadatain[] = ( data_a[0..0]);
	ram_block1a[97].portadatain[] = ( data_a[1..1]);
	ram_block1a[98].portadatain[] = ( data_a[2..2]);
	ram_block1a[99].portadatain[] = ( data_a[3..3]);
	ram_block1a[100].portadatain[] = ( data_a[4..4]);
	ram_block1a[101].portadatain[] = ( data_a[5..5]);
	ram_block1a[102].portadatain[] = ( data_a[6..6]);
	ram_block1a[103].portadatain[] = ( data_a[7..7]);
	ram_block1a[104].portadatain[] = ( data_a[8..8]);
	ram_block1a[105].portadatain[] = ( data_a[9..9]);
	ram_block1a[106].portadatain[] = ( data_a[10..10]);
	ram_block1a[107].portadatain[] = ( data_a[11..11]);
	ram_block1a[108].portadatain[] = ( data_a[12..12]);
	ram_block1a[109].portadatain[] = ( data_a[13..13]);
	ram_block1a[110].portadatain[] = ( data_a[14..14]);
	ram_block1a[111].portadatain[] = ( data_a[15..15]);
	ram_block1a[112].portadatain[] = ( data_a[16..16]);
	ram_block1a[113].portadatain[] = ( data_a[17..17]);
	ram_block1a[114].portadatain[] = ( data_a[18..18]);
	ram_block1a[115].portadatain[] = ( data_a[19..19]);
	ram_block1a[116].portadatain[] = ( data_a[20..20]);
	ram_block1a[117].portadatain[] = ( data_a[21..21]);
	ram_block1a[118].portadatain[] = ( data_a[22..22]);
	ram_block1a[119].portadatain[] = ( data_a[23..23]);
	ram_block1a[120].portadatain[] = ( data_a[24..24]);
	ram_block1a[121].portadatain[] = ( data_a[25..25]);
	ram_block1a[122].portadatain[] = ( data_a[26..26]);
	ram_block1a[123].portadatain[] = ( data_a[27..27]);
	ram_block1a[124].portadatain[] = ( data_a[28..28]);
	ram_block1a[125].portadatain[] = ( data_a[29..29]);
	ram_block1a[126].portadatain[] = ( data_a[30..30]);
	ram_block1a[127].portadatain[] = ( data_a[31..31]);
	ram_block1a[128].portadatain[] = ( data_a[0..0]);
	ram_block1a[129].portadatain[] = ( data_a[1..1]);
	ram_block1a[130].portadatain[] = ( data_a[2..2]);
	ram_block1a[131].portadatain[] = ( data_a[3..3]);
	ram_block1a[132].portadatain[] = ( data_a[4..4]);
	ram_block1a[133].portadatain[] = ( data_a[5..5]);
	ram_block1a[134].portadatain[] = ( data_a[6..6]);
	ram_block1a[135].portadatain[] = ( data_a[7..7]);
	ram_block1a[136].portadatain[] = ( data_a[8..8]);
	ram_block1a[137].portadatain[] = ( data_a[9..9]);
	ram_block1a[138].portadatain[] = ( data_a[10..10]);
	ram_block1a[139].portadatain[] = ( data_a[11..11]);
	ram_block1a[140].portadatain[] = ( data_a[12..12]);
	ram_block1a[141].portadatain[] = ( data_a[13..13]);
	ram_block1a[142].portadatain[] = ( data_a[14..14]);
	ram_block1a[143].portadatain[] = ( data_a[15..15]);
	ram_block1a[144].portadatain[] = ( data_a[16..16]);
	ram_block1a[145].portadatain[] = ( data_a[17..17]);
	ram_block1a[146].portadatain[] = ( data_a[18..18]);
	ram_block1a[147].portadatain[] = ( data_a[19..19]);
	ram_block1a[148].portadatain[] = ( data_a[20..20]);
	ram_block1a[149].portadatain[] = ( data_a[21..21]);
	ram_block1a[150].portadatain[] = ( data_a[22..22]);
	ram_block1a[151].portadatain[] = ( data_a[23..23]);
	ram_block1a[152].portadatain[] = ( data_a[24..24]);
	ram_block1a[153].portadatain[] = ( data_a[25..25]);
	ram_block1a[154].portadatain[] = ( data_a[26..26]);
	ram_block1a[155].portadatain[] = ( data_a[27..27]);
	ram_block1a[156].portadatain[] = ( data_a[28..28]);
	ram_block1a[157].portadatain[] = ( data_a[29..29]);
	ram_block1a[158].portadatain[] = ( data_a[30..30]);
	ram_block1a[159].portadatain[] = ( data_a[31..31]);
	ram_block1a[160].portadatain[] = ( data_a[0..0]);
	ram_block1a[161].portadatain[] = ( data_a[1..1]);
	ram_block1a[162].portadatain[] = ( data_a[2..2]);
	ram_block1a[163].portadatain[] = ( data_a[3..3]);
	ram_block1a[164].portadatain[] = ( data_a[4..4]);
	ram_block1a[165].portadatain[] = ( data_a[5..5]);
	ram_block1a[166].portadatain[] = ( data_a[6..6]);
	ram_block1a[167].portadatain[] = ( data_a[7..7]);
	ram_block1a[168].portadatain[] = ( data_a[8..8]);
	ram_block1a[169].portadatain[] = ( data_a[9..9]);
	ram_block1a[170].portadatain[] = ( data_a[10..10]);
	ram_block1a[171].portadatain[] = ( data_a[11..11]);
	ram_block1a[172].portadatain[] = ( data_a[12..12]);
	ram_block1a[173].portadatain[] = ( data_a[13..13]);
	ram_block1a[174].portadatain[] = ( data_a[14..14]);
	ram_block1a[175].portadatain[] = ( data_a[15..15]);
	ram_block1a[176].portadatain[] = ( data_a[16..16]);
	ram_block1a[177].portadatain[] = ( data_a[17..17]);
	ram_block1a[178].portadatain[] = ( data_a[18..18]);
	ram_block1a[179].portadatain[] = ( data_a[19..19]);
	ram_block1a[180].portadatain[] = ( data_a[20..20]);
	ram_block1a[181].portadatain[] = ( data_a[21..21]);
	ram_block1a[182].portadatain[] = ( data_a[22..22]);
	ram_block1a[183].portadatain[] = ( data_a[23..23]);
	ram_block1a[184].portadatain[] = ( data_a[24..24]);
	ram_block1a[185].portadatain[] = ( data_a[25..25]);
	ram_block1a[186].portadatain[] = ( data_a[26..26]);
	ram_block1a[187].portadatain[] = ( data_a[27..27]);
	ram_block1a[188].portadatain[] = ( data_a[28..28]);
	ram_block1a[189].portadatain[] = ( data_a[29..29]);
	ram_block1a[190].portadatain[] = ( data_a[30..30]);
	ram_block1a[191].portadatain[] = ( data_a[31..31]);
	ram_block1a[192].portadatain[] = ( data_a[0..0]);
	ram_block1a[193].portadatain[] = ( data_a[1..1]);
	ram_block1a[194].portadatain[] = ( data_a[2..2]);
	ram_block1a[195].portadatain[] = ( data_a[3..3]);
	ram_block1a[196].portadatain[] = ( data_a[4..4]);
	ram_block1a[197].portadatain[] = ( data_a[5..5]);
	ram_block1a[198].portadatain[] = ( data_a[6..6]);
	ram_block1a[199].portadatain[] = ( data_a[7..7]);
	ram_block1a[200].portadatain[] = ( data_a[8..8]);
	ram_block1a[201].portadatain[] = ( data_a[9..9]);
	ram_block1a[202].portadatain[] = ( data_a[10..10]);
	ram_block1a[203].portadatain[] = ( data_a[11..11]);
	ram_block1a[204].portadatain[] = ( data_a[12..12]);
	ram_block1a[205].portadatain[] = ( data_a[13..13]);
	ram_block1a[206].portadatain[] = ( data_a[14..14]);
	ram_block1a[207].portadatain[] = ( data_a[15..15]);
	ram_block1a[208].portadatain[] = ( data_a[16..16]);
	ram_block1a[209].portadatain[] = ( data_a[17..17]);
	ram_block1a[210].portadatain[] = ( data_a[18..18]);
	ram_block1a[211].portadatain[] = ( data_a[19..19]);
	ram_block1a[212].portadatain[] = ( data_a[20..20]);
	ram_block1a[213].portadatain[] = ( data_a[21..21]);
	ram_block1a[214].portadatain[] = ( data_a[22..22]);
	ram_block1a[215].portadatain[] = ( data_a[23..23]);
	ram_block1a[216].portadatain[] = ( data_a[24..24]);
	ram_block1a[217].portadatain[] = ( data_a[25..25]);
	ram_block1a[218].portadatain[] = ( data_a[26..26]);
	ram_block1a[219].portadatain[] = ( data_a[27..27]);
	ram_block1a[220].portadatain[] = ( data_a[28..28]);
	ram_block1a[221].portadatain[] = ( data_a[29..29]);
	ram_block1a[222].portadatain[] = ( data_a[30..30]);
	ram_block1a[223].portadatain[] = ( data_a[31..31]);
	ram_block1a[224].portadatain[] = ( data_a[0..0]);
	ram_block1a[225].portadatain[] = ( data_a[1..1]);
	ram_block1a[226].portadatain[] = ( data_a[2..2]);
	ram_block1a[227].portadatain[] = ( data_a[3..3]);
	ram_block1a[228].portadatain[] = ( data_a[4..4]);
	ram_block1a[229].portadatain[] = ( data_a[5..5]);
	ram_block1a[230].portadatain[] = ( data_a[6..6]);
	ram_block1a[231].portadatain[] = ( data_a[7..7]);
	ram_block1a[232].portadatain[] = ( data_a[8..8]);
	ram_block1a[233].portadatain[] = ( data_a[9..9]);
	ram_block1a[234].portadatain[] = ( data_a[10..10]);
	ram_block1a[235].portadatain[] = ( data_a[11..11]);
	ram_block1a[236].portadatain[] = ( data_a[12..12]);
	ram_block1a[237].portadatain[] = ( data_a[13..13]);
	ram_block1a[238].portadatain[] = ( data_a[14..14]);
	ram_block1a[239].portadatain[] = ( data_a[15..15]);
	ram_block1a[240].portadatain[] = ( data_a[16..16]);
	ram_block1a[241].portadatain[] = ( data_a[17..17]);
	ram_block1a[242].portadatain[] = ( data_a[18..18]);
	ram_block1a[243].portadatain[] = ( data_a[19..19]);
	ram_block1a[244].portadatain[] = ( data_a[20..20]);
	ram_block1a[245].portadatain[] = ( data_a[21..21]);
	ram_block1a[246].portadatain[] = ( data_a[22..22]);
	ram_block1a[247].portadatain[] = ( data_a[23..23]);
	ram_block1a[248].portadatain[] = ( data_a[24..24]);
	ram_block1a[249].portadatain[] = ( data_a[25..25]);
	ram_block1a[250].portadatain[] = ( data_a[26..26]);
	ram_block1a[251].portadatain[] = ( data_a[27..27]);
	ram_block1a[252].portadatain[] = ( data_a[28..28]);
	ram_block1a[253].portadatain[] = ( data_a[29..29]);
	ram_block1a[254].portadatain[] = ( data_a[30..30]);
	ram_block1a[255].portadatain[] = ( data_a[31..31]);
	ram_block1a[255..0].portare = B"1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111";
	ram_block1a[255..0].portawe = ( decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..7], decode3.eq[7..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..6], decode3.eq[6..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..5], decode3.eq[5..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..4], decode3.eq[4..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
	address_a_sel[2..0] = address_a[15..13];
	address_a_wire[] = address_a[];
	q_a[] = mux2.result[];
END;
--VALID FILE
