{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1498586726965 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition " "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1498586726965 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 27 20:05:26 2017 " "Processing started: Tue Jun 27 20:05:26 2017" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1498586726965 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586726965 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta NIOS_LED -c NIOS_LED " "Command: quartus_sta NIOS_LED -c NIOS_LED" {  } {  } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586726965 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1498586727105 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727449 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727449 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727511 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727511 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "16 " "TimeQuest Timing Analyzer is analyzing 16 combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." {  } {  } 0 335093 "TimeQuest Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the TimeQuest Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727761 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498586727855 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498586727855 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498586727855 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1498586727855 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1498586727855 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727855 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/altera_reset_controller.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/altera_reset_controller.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727871 ""}
{ "Info" "ISTA_SDC_FOUND" "NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc " "Reading SDC File: 'NIOS_LED/synthesis/submodules/NIOS_LED_nios2_gen2_0_cpu.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727871 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586727902 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727902 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586727902 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727902 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498586727902 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727902 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586727902 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586727902 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727902 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1498586727902 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498586727933 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "TimeQuest Timing Analyzer" 0 0 1498586727933 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 45.988 " "Worst-case setup slack is 45.988" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727949 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   45.988               0.000 altera_reserved_tck  " "   45.988               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727949 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727949 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.360 " "Worst-case hold slack is 0.360" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727965 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.360               0.000 altera_reserved_tck  " "    0.360               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727965 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727965 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 97.739 " "Worst-case recovery slack is 97.739" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.739               0.000 altera_reserved_tck  " "   97.739               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727996 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.442 " "Worst-case removal slack is 1.442" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.442               0.000 altera_reserved_tck  " "    1.442               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727996 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.654 " "Worst-case minimum pulse width slack is 49.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.654               0.000 altera_reserved_tck  " "   49.654               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586727996 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586727996 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 196.881 ns " "Worst Case Available Settling Time: 196.881 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586728027 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586728027 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498586728027 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586728074 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF256C8GES " "Timing characteristics of device 10M08DAF256C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586728074 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729511 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586729730 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729730 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586729730 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729730 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498586729730 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729730 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586729730 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586729730 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729730 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.239 " "Worst-case setup slack is 46.239" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729746 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729746 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.239               0.000 altera_reserved_tck  " "   46.239               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729746 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729746 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.322 " "Worst-case hold slack is 0.322" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.322               0.000 altera_reserved_tck  " "    0.322               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729761 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 97.872 " "Worst-case recovery slack is 97.872" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   97.872               0.000 altera_reserved_tck  " "   97.872               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729761 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729761 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.292 " "Worst-case removal slack is 1.292" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729777 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729777 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.292               0.000 altera_reserved_tck  " "    1.292               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729777 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729777 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.679 " "Worst-case minimum pulse width slack is 49.679" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729793 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729793 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.679               0.000 altera_reserved_tck  " "   49.679               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586729793 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729793 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.092 ns " "Worst Case Available Settling Time: 197.092 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586729808 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586729808 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1498586729840 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk_clk " "Node: clk_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] clk_clk " "Register x7seg:hex7led_0\|counter_n_bit:U4\|counter\[14\] is being clocked by clk_clk" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586730105 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730105 "|NIOS_LED|clk_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Node: NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch x7seg:hex7led_0\|x_sig\[0\] NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\] " "Latch x7seg:hex7led_0\|x_sig\[0\] is being clocked by NIOS_LED_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo\|mem_used\[1\]" {  } {  } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1498586730105 ""}  } {  } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730105 "|NIOS_LED|NIOS_LED_mm_interconnect_0:mm_interconnect_0|altera_avalon_sc_fifo:hex7led_0_avalon_slave_0_agent_rsp_fifo|mem_used[1]"}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Design Software" 0 -1 1498586730105 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730105 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586730105 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1498586730105 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730105 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.705 " "Worst-case setup slack is 48.705" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730136 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   48.705               0.000 altera_reserved_tck  " "   48.705               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730136 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730136 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.151 " "Worst-case hold slack is 0.151" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730183 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.151               0.000 altera_reserved_tck  " "    0.151               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730183 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730183 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 99.014 " "Worst-case recovery slack is 99.014" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   99.014               0.000 altera_reserved_tck  " "   99.014               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730199 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.573 " "Worst-case removal slack is 0.573" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.573               0.000 altera_reserved_tck  " "    0.573               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730199 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730199 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.421 " "Worst-case minimum pulse width slack is 49.421" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730215 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730215 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.421               0.000 altera_reserved_tck  " "   49.421               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1498586730215 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730215 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds. " "Worst-Case MTBF of Design is 1e+09 years or 3.15e+16 seconds." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.781 ns " "Worst Case Available Settling Time: 198.781 ns" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions. " "Worst-Case MTBF values are calculated based on the worst-case silicon characteristics, with worst-case operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5 " "  - Under worst-case conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 1.5" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7 " "  - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 3.7" {  } {  } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1498586730230 ""}  } {  } 0 332114 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586730230 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586731308 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586731308 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 18 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "930 " "Peak virtual memory: 930 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1498586731480 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jun 27 20:05:31 2017 " "Processing ended: Tue Jun 27 20:05:31 2017" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1498586731480 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1498586731480 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1498586731480 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1498586731480 ""}
