----------------------------------------------------------------------------------
-- PROTON
-- 
-- spina wszystkie komponenty w jeden moduł do obsługi 4 wyświetlaczy 7 seg
-- AVALON SLAVE INTERFACE
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity x7seg is
	port ( 
		x          : in STD_LOGIC_VECTOR (15 downto 0);
		clk        : in STD_LOGIC;
		resetn     : in STD_LOGIC;
		write      : in STD_LOGIC;
		chipselect : in STD_LOGIC;
		byteenable : in STD_LOGIC_VECTOR(1 DOWNTO 0);
		seg        : out  STD_LOGIC_VECTOR (7 downto 0);
		dig        : out  STD_LOGIC_VECTOR (3 downto 0));
end x7seg;

architecture logic of x7seg is

signal mux2decode : STD_LOGIC_VECTOR(3 downto 0);
signal ssel       : STD_LOGIC_VECTOR(1 downto 0);
signal be         : STD_LOGIC_VECTOR(1 downto 0);
signal x_sig      : STD_LOGIC_VECTOR (15 downto 0);

component mux16n4 is
	port ( x : in  STD_LOGIC_VECTOR (15 downto 0);
		sel : in  STD_LOGIC_VECTOR (1 downto 0);
		y : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

component hex7seg is
	port ( x : in  STD_LOGIC_VECTOR (3 downto 0);
		y : out  STD_LOGIC_VECTOR (6 downto 0));
end component;

component demux4n1 is
	port ( sel : in  STD_LOGIC_VECTOR (1 downto 0);
		an : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

component counter_n_bit is
	port ( clk : in  STD_LOGIC;
		sel : out  STD_LOGIC_VECTOR (1 downto 0));
end component;

begin
	
	with (chipselect and write) SELECT
		be <= byteenable WHEN '1', "00" WHEN OTHERS;

process(clk,resetn)

begin
	if resetn = '0' then
		x_sig <=  X"0000";
		seg(7) <= '1';
	else
		seg(7) <= '0';
		if be(0) = '1' then	x_sig(7 downto 0) <= x(7 downto 0); end if;
		if be(1) = '1' then	x_sig(15 downto 8) <= x(15 downto 8); end if;
	end if;

end process;

U1: mux16n4 port map ( x => x_sig, sel => ssel, y => mux2decode );
U2: hex7seg port map ( x => mux2decode, y => seg(6 downto 0) );
U3: demux4n1 port map ( sel => ssel, an => dig );
U4: counter_n_bit port map (clk => clk, sel => ssel );

end logic;

